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| Number | Title | Issue Date |
| 8120114 | Transistor having an etch stop layer including a metal compound that is selectively formed over a metal gate In one aspect, an apparatus may include a metal gate of a transistor. An etch stop layer may be selectively formed over the metal gate. The etch stop layer may include a metal compound. An insulating layer may be over the etch stop layer. A conductive structure may ... | 02/21/2012 |
| 8102003 | Resistance memory element, method of manufacturing resistance memory element and semiconductor memory device A resistance memory element which memorizes a high resistance state and a low resistance state and is switched between the high resistance state and the low resistance state by an application of a voltage includes a first electrode layer of titanium nitride film, a ... | 01/24/2012 |
| 7902605 | Resistor in an integrated circuit A resistive element having two vertical resistive portions placed in two holes formed in the upper portion of a substrate and a horizontal resistive portion placed in a buried cavity connecting the bottoms of the holes. ... | 03/08/2011 |
| 7425736 | Silicon layer with high resistance and fabricating method thereof A silicon layer with high resistance is provided. The silicon layer with high resistance is positioned on a substrate. Also, the silicon layer with high resistance includes a plurality of silicon material layers, and an interface layer between every two of the silic... | 09/16/2008 |
| 7391084 | LDMOS transistor device, integrated circuit, and fabrication method thereof An LDMOS transistor device in an integrated circuit comprises a semiconductor substrate (10), a gate region (1) including a gate semiconductor layer region (2; 2′; 151) on top of a gate insulation layer region (3; 141), source (4... | 06/24/2008 |
| 7348654 | Capacitor and inductor scheme with e-fuse application RF devices formed in integrated circuit devices include a top metal level overlying a substrate. The top metal level comprises pads and portions of planned RF devices and an RF metal level overlying the top metal level completes the RF devices which may be an interc... | 03/25/2008 |
| 7342276 | Method and apparatus utilizing monocrystalline insulator A semiconductor device, including: a semiconductor material; a conductive element; and a substantially monocrystalline insulator disposed between the semiconductor material and the conductive eleme... | 03/11/2008 |
| 7329387 | Field-effect transistor, sensor using it, and production method thereof A sensor which has high measuring sensitivity and is excellent in response is provided by forming a porous film in a sensitive section of a field-effect transistor. It comprises a porous body, which is formed on a sensitive section (here, a gate insulating film) of ... | 02/12/2008 |
| 7279746 | High performance CMOS device structures and method of manufacture A semiconductor device structure includes at least two field effect transistors formed on same substrate, the first field effect transistor includes a spacer having a first width, the second field effect transistor includes a compressive spacer having a second width... | 10/09/2007 |
| 7217657 | Semiconductor device having different metal silicide portions and method for fabricating the semiconductor device A method is disclosed in which differing metal layers are sequentially deposited on silicon-containing regions so that the type and thickness of the metal layers may be adapted to specific characteristics of the underlying silicon-containing regions. Subsequently, a... | 05/15/2007 |
| 7198992 | Method of manufacturing a semiconductor device comprising doping steps using gate electrodes and resists as masks The present invention is characterized in that a semiconductor film containing a rare gas element is formed on a crystalline semiconductor film obtained by using a catalytic element via a barrier layer, and the catalytic element is moved from the crystalline semicon... | 04/03/2007 |
| 7179702 | Semiconductor device including metal insulator semiconductor field effect transistor and method of manufacturing the same A semiconductor device comprises a semiconductor substrate, an N-channel MISFET and a P-channel MISFET provided on the semiconductor substrate, each of the N- and P-channel MISFETs being isolated by an isolation region and having a gate insulating film, a first gate... | 02/20/2007 |
| 7129148 | Methods for manufacturing semiconductor devices and semiconductor devices having trench isolation regions A semiconductor device having trench isolation regions in which leaks are suppressed may be formed using the following steps. (a) Forming a trench 32 in a semiconductor layer 12; (b) forming a dielectric layer 40 that fills the trench 32;... | 10/31/2006 |
| 7122885 | Flip-chip packaging A semiconductor die mounted between an X-lead frame and a support structure without bonding wires or straps. A power enhancement mode junction field effect transistor (JFET) die having a top surface defining a drain, and a bottom surface having a first metalized reg... | 10/17/2006 |
| 7033873 | Methods of controlling gate electrode doping, and systems for accomplishing same The present invention is generally directed to various methods of controlling gate electrode doping, and various systems for accomplishing same. In one illustrative embodiment, the method disclosed herein comprises performing at least one process operation to form a... | 04/25/2006 |
| 7005716 | Dual metal gate process: metals and their silicides Methods for forming dual-metal gate CMOS transistors are described. An NMOS and a PMOS active area of a semiconductor substrate are separated by isolation regions. A metal layer is deposited over a gate dielectric layer in each active area. Silicon ions are implante... | 02/28/2006 |
| 6992916 | SRAM cell design with high resistor CMOS gate structure for soft error rate improvement A high resistor SRAM memory cell to reduce soft error rate includes a first inverter having an output as a first memory node, and a second inverter having an output as a second memory node. The second memory node is coupled to an input of the first inverter through ... | 01/31/2006 |
| 6963111 | Efficient pMOS ESD protection circuit A pMOS transistor (601) is located in an n-well (602) and has at least one gate (603). Transistor (601) is connected between power pad Vdd or I/O pad (604) and ground potential Vss (605). Gate (603) is connected to po... | 11/08/2005 |
| 6940132 | Semiconductor device and method of manufacturing the same A semiconductor device includes a semiconductor substrate having a first major surface and a second major surface, source and drain layers formed in the first major surface, a gate insulating film formed on the first major surface, a gate layer formed on the gate in... | 09/06/2005 |
| 6940133 | Integrated trim structure utilizing dynamic doping An integrated circuit trim structure includes a dopant source, a target trim element formed in proximity to the dopant source, and a conductive heating element. The heater element is formed in proximity to the dopant source and includes first and second terminals an... | 09/06/2005 |
| 6894365 | Semiconductor device having an integral resistance element A resistance element of a semiconductor device includes a first resistance pattern and a second resistance pattern formed adjacent to the first resistance pattern at a lower level, wherein the second resistance pattern is defined by the first resistance pattern in a... | 05/17/2005 |
| 6878579 | Semiconductor device and method of manufacturing the same An aspect of the present invention includes a first conductive type semiconductor region; a gate electrode formed on the first conductive type semiconductor region; a channel region formed immediately below the gate electrode in the first conductive type semiconduct... | 04/12/2005 |
| 6870224 | MOS transistor apparatus and method of manufacturing same When polycrystalline silicon germanium film is used for gate electrodes in a MOS transistor apparatus, there have been problems of reduced reliability in the gate insulating film, due to stress in the silicon germanium grains. Therefore, a polysilicon germanium film... | 03/22/2005 |
| 6870229 | Ultra-low power basic blocks and their uses The present invention relates to an ultra-low power (ULP) MOS diode. The diode has a first and a second terminal. It comprises an n-MOS transistor having a channel, a first N+ doped diffusion region at one extremity of the channel and a second N+ diffusion region at... | 03/22/2005 |
| 6858908 | Complementary transistors having respective gates formed from a metal and a corresponding metal-silicide A method of forming a first and second transistor. The method provides a semiconductor surface (20). The method also forms a gate dielectric (30) adjacent the semiconductor surface. Further, the method forms a first transistor gate electrode (90... | 02/22/2005 |
| 6838747 | Semiconductor device having resistive element formed of semiconductor film A dopant is ion-implanted into a second region (52) of a polycrystalline silicon film (50) for a resistive element (5). Nitrogen or the like is ion-implanted into a second region (62) of a polycrystalline silicon film (60) for a re... | 01/04/2005 |
| 6791106 | Semiconductor device and method of manufacturing the same An aspect of the present invention includes a first conductive type semiconductor region; a gate electrode formed on the first conductive type semiconductor region; a channel region formed immediately below the gate electrode in the first conductive type semiconduct... | 09/14/2004 |
| 6787850 | Dynamic threshold voltage MOS transistor fitted with a current limiter The invention concerns a semi-conductor device comprising on a substrate: a first dynamic threshold voltage MOS transistor (10), with a gate (116), and a channel (111) of a first conductivity type, and a current limiter means (2... | 09/07/2004 |
| 6750519 | Dual metal gate process: metals and their silicides Methods for forming dual-metal gate CMOS transistors are described. An NMOS and a PMOS active area of a semiconductor substrate are separated by isolation regions. A metal layer is deposited over a gate dielectric layer in each active area. Silicon ions are implante... | 06/15/2004 |
| 6670683 | Composite transistor having a slew-rate control A metal oxide semiconductor transistor having a slew-rate control is disclosed. The transistor having a slew-rate control includes an elongated diffusion area and an elongated gate overlying the diffusion area. The elongated diffusion area has at least tw... | 12/30/2003 |
| 6646309 | Electrostatic discharge trigger Employing an electrostatic discharge (ESD) trigger to trigger the MOS transistors (i.e., the ESD fingers) within a CMOS device to provide substantially more uniform turn-on voltages for the MOS transistors, resulting in better ESD device performance witho... | 11/11/2003 |
| 6646324 | Method and apparatus for a linearized output driver and terminator A method and apparatus for a linearized output driver and terminator is described. In one embodiment the method includes forming a gate electrode on a substrate, the portion of the substrate covered by the gate electrode defining a channel. The method fur... | 11/11/2003 |
| 6627957 | Semiconductor device and fabrication method thereof To provide a semiconductor device restraining high frequency impedance and restraining deterioration of a semiconductor layer, a gate wiring 26 is extended while meandering and intersects with a substantially straight line portion of a semiconductor layer... | 09/30/2003 |
| 6617632 | Semiconductor device and a method of manufacturing the same A parallel connection-type nonvolatile memory semiconductor device comprises a plurality of memory cells disposed on a semiconductor substrate in matrix form, each including a gate insulating film, a floating gate electrode, an interlayer film and a contr... | 09/09/2003 |
| 6614061 | Electrostatic discharge-protection semiconductor device The present invention provides an electrostatic discharge-protection device located between a pad and a specific voltage point. The electrostatic discharge-protection device has a P-type substrate. Then a first N-type well, a first P-type doped region, an... | 09/02/2003 |
| 6580108 | Insulated gate bipolar transistor decreasing the gate resistance An insulated gate transistor comprising a first semiconductor region, a second semiconductor region includes plural portions, a third semiconductor region, a fourth semiconductor region, a first insulation layer, control electrodes, a first main electrode... | 06/17/2003 |
| 6566717 | Integrated circuit with silicided ESD protection transistors An electrostatic discharge (ESD) protection circuit for protecting an internal device from an ESD is disclosed. The ESD protection circuit includes an NMOS transistor connected to a ground voltage terminal having silicide layers on a gate electrode and on... | 05/20/2003 |
| 6521943 | Semiconductor device having thin electrode layer adjacent gate insulator and method of manufacture Disclosed is a semiconductor device (e.g., nonvolatile semiconductor memory device) and method of forming the device. The device includes a gate electrode (e.g., floating gate electrode) having a first layer of an amorphous silicon film, or a polycrystall... | 02/18/2003 |
| 6507072 | Insulated gate field effect semiconductor device and forming method thereof In an insulated gate field effect semiconductor device, the gate electrode formed on the gate insulating film includes the first and second semiconductor layers as a double layer. An impurity for providing one conductivity type is not contained in first s... | 01/14/2003 |
| 6469351 | Electrostatic breakdown prevention circuit for semiconductor device A Vss-side off transistor is often used in an electrostatic breakdown prevention circuit having an NMOS transistor. In such a circuit, the state of connection of the transistor ensures that off-leak current has a significant influence on the standby curre... | 10/22/2002 |
