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| Number | Title | Issue Date |
| 8008727 | Semiconductor integrated circuit device including a pad and first mosfet To reduce the leak current in the MOSFET connected between the pad and the ground. There are provided a pad PAD for an input or output signal, an n-type MOSFET M1a connected between the pad PAD and the ground and having its gate terminal and backgate c... | 08/30/2011 |
| 7696575 | Semiconductor device and method of manufacture thereof A semiconductor device of complementary structure with increased carrier mobilities of both polarities by applying orientation-dependent mechanical stresses to their respective semiconductor channel regions, comprises a semiconductor region subjected to compressive ... | 04/13/2010 |
| 7687860 | Semiconductor device including impurity regions having different cross-sectional shapes There are provided a memory transistor having a select transistor with asymmetric gate electrode structure and an inverted T-shaped floating gates and a method for forming the same. A gate electrode of the select transistor adjacent to a memory transistor has substa... | 03/30/2010 |
| 7622776 | Semiconductor device A semiconductor device includes: a substrate including a compound semiconductor, a semiconductor layer formed on a surface of the substrate, a plurality of gate electrodes formed on the semiconductor layer, a plurality of source electrodes formed on the semiconducto... | 11/24/2009 |
| 7554160 | Semiconductor device A semiconductor device has a source region, a channel region and a drain region formed in order along a surface of a substrate, a vertical type bipolar transistor formed from the source region below the substrate, a base contact region of the vertical type bipolar t... | 06/30/2009 |
| 7541648 | Electrostatic discharge (ESD) protection circuit An electrostatic discharge (ESD) protection circuit that includes a parallel connection of parasitic vertical and lateral bipolar junction transistors (BJTs) each with a floating base and a metal oxide semiconductor (MOS) field transistor with a floating body is dis... | 06/02/2009 |
| 7538395 | Method of forming low capacitance ESD device and structure therefor In one embodiment, the ESD device uses highly doped P and N regions deep within the ESD device to form a zener diode that has a controlled breakdown voltage. ... | 05/26/2009 |
| 7465995 | Resistor structure for ESD protection circuits A semiconductor device includes an ESD protection device on a substrate, and a resistor having a gate structure overlying a resistor well separating a first doped region coupled to the ESD protection device and a second doped region coupled to a supply voltage for p... | 12/16/2008 |
| 7405445 | Semiconductor structure and method for ESD protection A semiconductor integrated circuit structure includes a plurality of diodes disposed in the substrate. These diodes are electrically coupled in series. At least one insertion region is disposed in the substrate between two of the diodes and a supply voltage node ele... | 07/29/2008 |
| 7405446 | Electrostatic protection systems and methods Systems and methods are disclosed herein to provide improved electrostatic protection for electrical circuits. For example, in accordance with an embodiment of the present invention, an electrostatic protection device includes: a drain region formed in a substrate; ... | 07/29/2008 |
| 7385254 | Structure for protection against radio disturbances A structure of protection of a first area of a semiconductor wafer including a substrate of a first conductivity type against high-frequency noise likely to be injected from components formed in the upper portion of a second area of the wafer, includes a very heavil... | 06/10/2008 |
| 7372495 | CMOS aps with stacked avalanche multiplication layer and low voltage readout electronics An image sensor includes a pixel having a protection circuit connected to a charge multiplying photoconversion layer. The protection circuit prevents the pixel circuit from breaking down when the voltage in the pixel circuit reaches the operating voltage applied to ... | 05/13/2008 |
| 7361966 | Actuator chip for inkjet printhead with electrostatic discharge protection An inkjet printhead chip includes electrostatic discharge (ESD) circuits to protect the chip during ESD events, including one preventing a thin dielectric layer on a substrate from breakdown. In one embodiment, the chip includes an ESD circuit essentially dedicated ... | 04/22/2008 |
| 7361957 | Device for electrostatic discharge protection and method of manufacturing the same The present invention relates to a device for electrostatic discharge protection (ESD). According to an embodiment of the present invention, a device for electrostatic discharge protection includes a semiconductor substrate, a plurality of field oxide films formed i... | 04/22/2008 |
| 7355250 | Electrostatic discharge device with controllable holding current An electrostatic discharge (ESD) device with a parasitic silicon controlled rectifier (SCR) structure and controllable holding current is provided. A first distance is kept between a first N+ doped region and a first P+ doped region, and a second distance is kept be... | 04/08/2008 |
| 7352032 | Output driver with split pins The drains of the PMOS transistor and the NMOS transistor of a driver are separated and connected to two spaced-apart pins. The spaced-apart pins provide ESD protection to the NMOS transistor, which can be turned on during an ESD event by voltages that propagate thr... | 04/01/2008 |
| 7342281 | Electrostatic discharge protection circuit using triple welled silicon controlled rectifier Provided is an electrostatic discharge (ESD) protection circuit using a silicon controlled rectifier (SCR), which is applied to a semiconductor integrated circuit (IC). A semiconductor substrate has a triple well structure such that a bias is applied to a p-well cor... | 03/11/2008 |
| 7340699 | Analysis apparatus for semiconductor LSI circuit electrostatic discharge by calculating inter-pad voltage between pads A semiconductor integrated circuit electrostatic discharge analysis apparatus includes a resistance network generation unit generating a resistance network served as a power supply interconnect equivalent circuit in a logic cell region of a semiconductor LSI circuit... | 03/04/2008 |
| 7332778 | Semiconductor device and method of manufacturing same To refine a semiconductor device (100), in particular a S[ilicon]O[n]I[nsulator] device, comprising: at least one isolating layer (10) made of a dielectric material; at least one silicon substrate ( | 02/19/2008 |
| 7329925 | Device for electrostatic discharge protection A device for electrostatic discharge (ESD) protection is disclosed. The device for electrostatic discharge protection includes a lateral bipolar transistor and a diode. The semiconductor transistor has an emitter, a base and a collector electrically connected to a f... | 02/12/2008 |
| 7317228 | Optimization of NMOS drivers using self-ballasting ESD protection technique in fully silicided CMOS process Design and optimization of NMOS drivers using a self-ballasting ESD protection technique in a fully silicided CMOS process. Silicided NMOS fingers which include segmented drain diffusion. Specifically, the segmented drain diffusion provides self-ballasting resistors... | 01/08/2008 |
| 7309897 | Electrostatic discharge protector for an integrated circuit An integrated circuit has functional circuitry coupled to a terminal. An electrostatic discharge protector can be coupled to the terminal to protect the functional circuitry from an electrostatic discharge. A substrate includes a first semiconductor material with a ... | 12/18/2007 |
| 7309883 | Semiconductor device capable of preventing current flow caused by latch-up and method of forming the same A semiconductor device includes first, second, and third wells. The first well is connected to a pad to which an external pin is connected and includes a first-type diffusion region that receives a well bias voltage. The second well is adjacent to the first well, an... | 12/18/2007 |
| 7291887 | Protection circuit for electrostatic discharge A protection circuit protects an integrated circuit (“IC”) from peak voltages and includes a voltage divider coupled to a silicon controlled rectifier. The voltage divider allows for adjustment of the trigger voltage, trigger current, and holding voltage of the ... | 11/06/2007 |
| 7291888 | ESD protection circuit using a transistor chain An electrostatic discharge (ESD) protection circuit for dissipating an ESD current from a first pad to a second pad during an ESD event. The ESD protection circuit includes a first bipolar transistor having an emitter coupled to the first pad. A second bipolar trans... | 11/06/2007 |
| 7285827 | Back-to-back NPN/PNP protection diodes A device includes a memory device and an NPN or PNP diode coupled to a word-line of the memory device. The NPN or PNP diode reduces device damage and performance impairment that may result from device charging by drawing charges away from the memory device. ... | 10/23/2007 |
| 7279753 | Floating base bipolar ESD devices The present invention includes a bipolar ESD device for protecting an integrated circuit from ESD damage. The bipolar ESD device includes a collector connected to a terminal of the integrated circuit, a floating base, and a grounded emitter. When an ESD pulse hits t... | 10/09/2007 |
| 7274071 | Electrostatic damage protection device with protection transistor This invention provides an electrostatic damage protection device which can protects a device to be protected enough from an electrostatic damage and prevents damages of protection transistors themselves. A N-channel type first MOS transistor and a N-channel type se... | 09/25/2007 |
| 7268398 | ESD protection cell with active pwell resistance control In an NMOS device, the turn-on voltage or the triggering voltage is reduced by adding an NBL connected to an n-sinker and contacted through an n+ region, which is connected to a bias voltage. The bias voltage may be provided by the drain contact or by a separate bia... | 09/11/2007 |
| 7256976 | Electrostatic discharge protective circuit and semiconductor integrated circuit using the same An electrostatic discharge protective circuit including an ESD protective circuit which has a trigger terminal and forms a discharge path from a first node to a second node when trigger signals are supplied to the trigger terminal, a trigger circuit included in a ci... | 08/14/2007 |
| 7256461 | Electrostatic discharge (ESD) protection device The present invention provides a combinded FOX and poly gate structure, for effectively reducing the trigger voltage of a conventional field device, for improving the robustness of a NMOS transistor of a small drive I/O circuit, and for improving the ESD performance... | 08/14/2007 |
| 7250660 | ESD protection that supports LVDS and OCT Circuits are described that provide electrostatic discharge protection for I/O circuits that support the low voltage differential signaling (LVDS) and on-chip termination (OCT) standards. At least one additional transistor is connected across an I/O transistor. In t... | 07/31/2007 |
| 7226835 | Versatile system for optimizing current gain in bipolar transistor structures Disclosed are apparatus and methods for designing electrical contact for a bipolar emitter structure. The area of an emitter structure (106, 306, 400, 404) and the required current density throughput of an electrical contact structure (108, 308, 402, 406 | 06/05/2007 |
| 7217980 | CMOS silicon-control-rectifier (SCR) structure for electrostatic discharge (ESD) protection An electrostatic discharge protection device, including a silicon-control-rectifier, in complementary metal-oxide semiconductor (CMOS) process is disclosed. in one embodiment of the present invention, the protection device includes a semiconductor substrate having a... | 05/15/2007 |
| 7215005 | Bipolar ESD protection structure The invention describes the fabrication and structure of an ESD protection device for integrated circuit semiconductor devices with improved ESD protection and resiliency. A vertical bipolar npn transistor forms the basis of the protection device. To handle the larg... | 05/08/2007 |
| 7211868 | Protection circuit device using MOSFETs and a method of manufacturing the same A protection circuit device using a MOSFET has a plural of conductive paths separated electrically, a MOSFET chip integrating two power MOSFETs in one chip where a gate electrode and a source electrode are fixed on the desired conductive path, conductive material pr... | 05/01/2007 |
| 7205612 | Fully silicided NMOS device for electrostatic discharge protection A device and method are described for forming a grounded gate NMOS (GGNMOS) device used to provide protection against electrostatic discharge (ESD) in an integrated circuit (IC). The device is achieved by adding n-wells below the source and drain regions. By tailori... | 04/17/2007 |
| 7205613 | Insulating substrate for IC packages having integral ESD protection An IC package substrate having integral ESD protection features and elements and a method for construction of the same are disclosed ... | 04/17/2007 |
| 7202531 | Semiconductor device A semiconductor device includes an output pad and a surge absorption unit formed above a semiconductor region of a first conductivity type. The surge absorption unit includes: a semiconductor island region of a second conductivity type; a buried layer of the second ... | 04/10/2007 |
| 7196369 | Plasma damage protection circuit for a semiconductor device A protection device and a method for manufacturing integrated circuit devices protect against plasma charge damage, and related charge damage during manufacture. The protection device comprises a dynamic threshold, NMOS/PMOS pair having their respective gate termina... | 03/27/2007 |
