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| Number | Title | Issue Date |
| 8183638 | Dual triggered silicon controlled rectifier A dual triggered silicon controlled rectifier (DTSCR) comprises: a semiconductor substrate; a well region, a first N+ diffusion region, a first P+ diffusion region, a second N+ diffusion region, a second P+ diffusion region, a third P+ diffusion region, positioned i... | 05/22/2012 |
| 8169028 | Semiconductor device In a conventional semiconductor device, protection of a to-be-protected element from a surge voltage is difficult because the to-be-protected element is turned on before a protection element due to variations in manufacturing conditions. In a semiconductor device of... | 05/01/2012 |
| 8102002 | System and method for isolated NMOS-based ESD clamp cell The invention is directed to a protection circuit for protecting IC chips against ESD. An ESD protection circuit for an integrated circuit chip may comprise an isolated NMOS transistor, which may comprise an isolation region isolating a backgate from a substrate, an... | 01/24/2012 |
| 8089127 | Dual triggered silicon controlled rectifier A dual triggered silicon controlled rectifier (DTSCR) comprises: a semiconductor substrate; an N-well, a P-well, a first N+ diffusion region and a first P+ diffusion region, a second N+ diffusion region and a second P+ diffusion region, a third P+ diffusion region, ... | 01/03/2012 |
| 8026552 | Protection element and fabrication method for the same The protection element of the present invention is constructed of a MOS capacitor composed of a semiconductor substrate, an insulating film formed on the semiconductor substrate and a word line formed on the insulating film. A well region having a conductivity type ... | 09/27/2011 |
| 8018002 | Field effect resistor for ESD protection An electrostatic discharge protection device and methodology are provided for protecting semiconductor devices against electrostatic discharge events by temporarily forming during normal (non-ESD) operation two more inversion layers (112, 113) in a first well... | 09/13/2011 |
| 8015518 | Structures for electrostatic discharge protection for bipolar semiconductor circuitry A design structure for electrostatic discharge protection comprises a first data representing a first electrostatic discharge (ESD) protection circuit and a second data representing a second ESD protection circuit. A parallel connection of two ESD protection units, ... | 09/06/2011 |
| 8008725 | Field transistors for electrostatic discharge protection and methods for fabricating the same A field transistor for electrostatic discharge (ESD) protection and method for making such a transistor is described. The field transistor includes a gate conductive layer pattern formed on a field oxide layer. Since the gate conductive layer pattern is formed on th... | 08/30/2011 |
| 8008726 | Trig modulation electrostatic discharge (ESD) protection devices Trig modulation electrostatic discharge (ESD) protection devices are presented. An ESD protection device includes a semiconductor substrate. A high voltage N-well (HVNW) region is formed in the semiconductor substrate. An NDD region, a first P-body region and a seco... | 08/30/2011 |
| 7999324 | Semiconductor device including overcurrent protection element A semiconductor device includes first, second, third, and fourth semiconductor regions, a gate electrode, and silicide layers. The first, second, and third semiconductor regions are formed in a semiconductor substrate while being spaced part from each other. The fou... | 08/16/2011 |
| 7859056 | Apparatus and methods for integrated circuit with devices with body contact and devices with electrostatic discharge protection An integrated circuit (IC) includes one or more silicon-on-insulator (SOI) transistors. Each SOI transistor includes a first source region, a second source region, a drain region, a body contact region, a gate, and first and second isolation regions. The body contac... | 12/28/2010 |
| 7838941 | Electrostatic discharge protection device having a dual triggered transistor Disclosed is an electrostatic discharge protection device that has a low trigger voltage and protects an internal circuit from electrostatic discharge. The ESD protection device includes an NMOS transistor in which a first pad and a drain are connected to each other... | 11/23/2010 |
| 7834401 | Semiconductor device and fabrication method for the same The semiconductor device includes: memory cells each having a first multilayer electrode including a first lower electrode made of a first conductive film and a first upper electrode made of a second conductive film formed one on the other with a first interface fil... | 11/16/2010 |
| 7821070 | Trig modulation electrostatic discharge (ESD) protection devices Trig modulation electrostatic discharge (ESD) protection devices are presented. An ESD protection device includes a semiconductor substrate. A high voltage N-well (HVNW) region is formed in the semiconductor substrate. An NDD region, a first P-body region and a seco... | 10/26/2010 |
| 7804135 | Integrated semiconductor diode arrangement and integrated semiconductor component An integrated semiconductor diode arrangement is provided. The arrangement includes an anode region and a cathode region that are formed in a semiconductor material region. The anode region has an arrangement of alternately occurring and directly adjacent first and ... | 09/28/2010 |
| 7800180 | Semiconductor electrostatic protection device A semiconductor device is disclosed. The semiconductor device includes an internal circuit having a high breakdown voltage transistor, and a first electrostatic protection circuit in which electrostatic protection elements are connected in series. The sum of the bre... | 09/21/2010 |
| 7777277 | Dual triggered silicon controlled rectifier The present invention provides a dual triggered silicon controlled rectifier (DTSCR) including: a semiconductor substrate, an N-well, a P-well, a first N+ diffusion region and a first P+ diffusion region, a second N+ diffusion region and a second P+ diffusion region... | 08/17/2010 |
| 7723794 | Load driving device A load driving device includes a drive control signal generation circuit generating a load drive control signal and a semiconductor buffer circuit generating an output signal in response to the load drive control signal. The buffer circuit has a pair of gate driven ... | 05/25/2010 |
| 7705404 | Electrostatic discharge protection device and layout thereof An electrostatic discharge (ESD) protection device and a layout thereof are provided. A bias conducting wire is mainly used to couple each base of a plurality of parasitic transistors inside ESD elements together, in order to simultaneously trigger all the parasitic... | 04/27/2010 |
| 7705403 | Programmable ESD protection structure In a LVTSCR or snapback NMOS ESD structure, low voltage protection as well as higher voltage protection is provided by introducing a floating gate that capacitively couples with the control gate of the ESD structure and programming the floating gate to have differen... | 04/27/2010 |
| 7671416 | Method and device for electrostatic discharge protection A device for providing electrostatic discharge (ESD) protection is provided. The device includes a semiconductor substrate having a drain, a source, and a gate formed therein. The drain contains a region having a resistance that is higher than the resistance of the ... | 03/02/2010 |
| 7667272 | Semiconductor device including a current mirror circuit In a semiconductor device, where, with respect to a parasitic resistor in a current mirror circuit, a compensation resistor for compensating the parasitic resistor is provided in the current mirror circuit, the current mirror circuit includes at least two thin film ... | 02/23/2010 |
| 7649229 | ESD protection device A semiconductor device capable of preventing an electrostatic surge without increasing a leak current. In the semiconductor device, a protection circuit for protecting an internal circuit is provided between a source line and a ground line. The protection circuit ha... | 01/19/2010 |
| 7557413 | Serpentine ballasting resistors for multi-finger ESD protection device This invention discloses a ballasting resistor for an electrostatic discharge (ESD) device that comprises at least one first active region forming a source/drain of an ESD discharge transistor, at least one resistive element with a serpentine shape formed in a singl... | 07/07/2009 |
| 7554159 | Electrostatic discharge protection device and method of manufacturing the same An electrostatic discharge protection device that includes a semiconductor substrate of a first dopant type, at least one source/drain pair of a second dopant type formed in the substrate, wherein the source/drain pair is separated to define a channel region therebe... | 06/30/2009 |
| 7514749 | Semiconductor device and a method of manufacturing the same A method of manufacturing a semiconductor integrated circuit device having on the same substrate both a high breakdown voltage MISFET and a low breakdown voltage MISFET is provided. An element isolation trench is formed in advance so that the width thereof is larger... | 04/07/2009 |
| 7508038 | ESD protection transistor An electrostatic discharge (ESD) transistor structure includes a self-aligned outrigger less than 0.4 microns from a gate electrode that is 50 microns wide. The outrigger is fabricated on ordinary logic transistors of an integrated circuit without severely affecting... | 03/24/2009 |
| 7473974 | Semiconductor circuit device including a protection circuit A protection element comprises a ring-shape gate electrode, an N+ drain region inside the ring-shape gate electrode, an N+ source region outside, and a shield plate electrode. The ring gate and source regions are connected to ground via a throu... | 01/06/2009 |
| 7465994 | Layout structure for ESD protection circuits A layout structure for an ESD protection circuit includes a first MOS device area having a first and second doped regions of the same polarity disposed at two sides of a first conductive gate layer, and a third doped region disposed along the first doped region at o... | 12/16/2008 |
| 7456478 | MOS transistor circuit A reduction of a current capability of a MOS transistor (P1) is compensated by dynamically changing a substrate bias of the MOS transistor (P1) in response to a fluctuation of the power supply, and thus an operating speed is stabilized automatically. A... | 11/25/2008 |
| 7439591 | Gate layer diode method and apparatus Method, apparatus, and article of manufacture for a diode defined by a portion of a gate layer of an integrated circuit. Illustrative, non-limiting embodiments of the invention are provided, including a temperature compensated DRAM, a temperature compensated CPU, a ... | 10/21/2008 |
| 7432555 | Testable electrostatic discharge protection circuits A semiconductor die has a bonding pad for a MOSFET such as a power MOSFET and a separate bonding pad for ESD protection circuitry. Connecting the bonding pads together makes the ESD protection circuitry functional to protect the MOSFET. Before connecting the bonding... | 10/07/2008 |
| 7420251 | Electrostatic discharge protection circuit and driving circuit for an LCD using the same An exemplary ESD protection circuit includes first and second sets of transistors and an ESD discharge transistor. Each of the transistors includes a source electrode, a drain electrode, and a gate electrode. The drain electrodes and gate electrodes of each of the t... | 09/02/2008 |
| 7417303 | System and method for ESD protection An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programable attenuation and a programable gain low noise amplifier. Frequency conversion circu... | 08/26/2008 |
| 7411251 | Self protecting NLDMOS, DMOS and extended voltage NMOS devices In an NLDMOS, DMOS or NMOS active device the ability to withstand snapback under stress conditions is provided by moving the hot spot away from the drain contact region. This is achieved by moving the drain contact region further away from the gate and including an ... | 08/12/2008 |
| 7408226 | Electronic card with protection against aerial discharge An electronic card includes a card terminal which is exposed on a surface of a card, a semiconductor integrated circuit chip including an insulated-gate field effect transistor, and a protection circuit which is provided between the card terminal and the insulated-g... | 08/05/2008 |
| 7405446 | Electrostatic protection systems and methods Systems and methods are disclosed herein to provide improved electrostatic protection for electrical circuits. For example, in accordance with an embodiment of the present invention, an electrostatic protection device includes: a drain region formed in a substrate; ... | 07/29/2008 |
| 7402869 | Apparatus and method for breakdown protection of a source follower circuit A breakdown protection circuit for a source follower comprising a field effect transistor (FET). The protection circuit comprises a plurality of PFET's and NFET's that are controlled to exhibit on and off states for advantageously configuring a gate, source, drain a... | 07/22/2008 |
| 7402846 | Electrostatic discharge (ESD) protection structure and a circuit using the same An electrostatic discharge (ESD) protection structure is disclosed. The ESD protection structure includes an active device. The active device includes a plurality of drains. Each of the drains has a contact row and at least one body contact row. The at least one bod... | 07/22/2008 |
| 7397089 | ESD protection structure using contact-via chains as ballast resistors According to an exemplary embodiment, an ESD protection structure situated in a semiconductor die includes a FET including a gate and first and second active regions, where the gate includes at least one gate finger, and where the at least one gate finger is situate... | 07/08/2008 |
