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| Number | Title | Issue Date |
| 8154083 | Semiconductor device formed on high-resistance substrate The present invention relates to a semiconductor device and a method of manufacturing the same. A high-resistance silicon wafer is manufactured in such a manner that a large-sized silicon wafer manufactured by the Czochralski method is irradiated with neutrons, and ... | 04/10/2012 |
| 8097921 | Semiconductor device with high-breakdown-voltage transistor A semiconductor device includes a high-breakdown-voltage transistor having a semiconductor layer. The semiconductor layer has an element portion and a wiring portion. The element portion has a first wiring on a front side of the semiconductor layer and a backside el... | 01/17/2012 |
| 8018001 | Semiconductor device A breakdown voltage of a clamp diode can be reduced while a leakage current is suppressed. A P− type diffusion layer is formed in a surface of an N− type semiconductor layer. An N+ type diffusion layer is formed in a surface of t... | 09/13/2011 |
| 7973365 | Integrated RF ESD protection for high frequency circuits The invention relates to a high-frequency integrated circuit requiring ESD protection for a circuit node. One or more metallic layer is deposited within the integrated circuit and patterned to form a transmission line. The metallic layers are generally already prese... | 07/05/2011 |
| 7948035 | Decoding system capable of charging protection for flash memory devices The present invention relates to a flash memory array. The flash memory array includes at least two word lines of gate electrode material. At least one of the word lines is connected through a first metal level to a discharge circuit, while other word line(s) may co... | 05/24/2011 |
| 7902604 | Configuration of gate to drain (GD) clamp and ESD protection circuit for power device breakdown protection A semiconductor power device supported on a semiconductor substrate comprising a plurality of transistor cells each having a source and a drain with a gate to control an electric current transmitted between the source and the drain. The semiconductor further include... | 03/08/2011 |
| 7728385 | Trench MOSFET with an ONO insulating layer sandwiched between an ESD protection module atop and a semiconductor substrate A device structure is disclosed for preventing gate oxide damage of a trench MOSFET during wafer processing while adding an ESD protection module atop the trench MOSFET. The ESD protection module has a low temperature oxide (LTO) bottom layer whose patterning proces... | 06/01/2010 |
| 7633125 | Integration of silicon boron nitride in high voltage and small pitch semiconductors Integration of silicon boron nitride in high voltage semiconductors is generally described. In one example, a microelectronic apparatus includes a semiconductor substrate upon which transistors of an integrated circuit are formed, a plurality of transistor gates for... | 12/15/2009 |
| 7612410 | Trigger device for ESD protection circuit The present invention is a trigger device useful, for example, in triggering an SCR in an ESD protection circuit. Illustratively, an NMOS trigger device comprises a gate and heavily doped P and N regions in a P-well on opposite sides of the gate. A first N type sour... | 11/03/2009 |
| 7579658 | Devices without current crowding effect at the finger's ends ESD protection devices without current crowding effect at the finger's ends. It is applied under MM ESD stress in sub-quarter-micron CMOS technology. The ESD discharging current path in the NMOS or PMOS device structure is changed by the proposed new structures, the... | 08/25/2009 |
| 7518192 | Asymmetrical layout structure for ESD protection A semiconductor structure for electrostatic discharge protection is presented. The semiconductor structure comprises a grounded gate nMOS (GGNMOS) having a substrate, a gate electrode, a source region and a drain region. A plurality of contact plugs is formed on the... | 04/14/2009 |
| 7470959 | Integrated circuit structures for preventing charging damage Disclosed is a circuit for preventing charging damage in an integrated circuit design, for example, a design having silicon over insulator (SOI) transistors. The circuit prevents damage from charging during processing to the gate of IC devices by assigning regions t... | 12/30/2008 |
| 7439590 | Semiconductor device A semiconductor device features connecting gate patterns of all transistors to a N+ or +P junction by the first connected wiring layer to prevent degradation of characteristics of the semiconductor device which results from plasma damages during a process. In order ... | 10/21/2008 |
| 7439591 | Gate layer diode method and apparatus Method, apparatus, and article of manufacture for a diode defined by a portion of a gate layer of an integrated circuit. Illustrative, non-limiting embodiments of the invention are provided, including a temperature compensated DRAM, a temperature compensated CPU, a ... | 10/21/2008 |
| 7436041 | Electrostatic discharge protection circuit using a double-triggered silicon controlling rectifier An ESD protection circuit using a double-triggered silicon controller rectifier (SCR). The double-triggered silicon controller rectifier (SCR) includes N+ diffusion areas, P+ diffusion areas, a first N-well region, a second N-well region and a third N-well region fo... | 10/14/2008 |
| 7432556 | Semiconductor device with dummy conductors At least a laminate of a gate insulating film 6 and a gate electrode 7 and an active region 13 are formed on a silicon substrate 1, and an underlying interlayer insulating film 10 is further formed. Then, a conductor 11a ... | 10/07/2008 |
| 7429774 | Electrostatic discharge (ESD) protection MOS device and ESD circuitry thereof An NMOS device having protection against electrostatic discharge. The NMOS device includes a P-substrate, a P-epitaxial layer overlying the P-substrate, a P-well in the P-epitaxial layer, an N-well in the P-epitaxial layer and encompassing the P-well, an N-Buried La... | 09/30/2008 |
| 7420252 | LDMOS device with improved ESD performance A semiconductor device includes a first doped region disposed on a first well in a semiconductor substrate; a second doped region disposed on a second well adjacent to the first well in the semiconductor substrate, the second doped region having a dopant density hig... | 09/02/2008 |
| 7420251 | Electrostatic discharge protection circuit and driving circuit for an LCD using the same An exemplary ESD protection circuit includes first and second sets of transistors and an ESD discharge transistor. Each of the transistors includes a source electrode, a drain electrode, and a gate electrode. The drain electrodes and gate electrodes of each of the t... | 09/02/2008 |
| 7417287 | Electrostatic discharge device having controllable trigger voltage An electrostatic discharge (ESD) device has a parasitic SCR structure and a controllable trigger voltage. The controllable trigger voltage of the ESD device is achieved by modulating a distance between an edge of a lightly doped well and an edge of a heavily doped r... | 08/26/2008 |
| 7417303 | System and method for ESD protection An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programable attenuation and a programable gain low noise amplifier. Frequency conversion circu... | 08/26/2008 |
| 7402846 | Electrostatic discharge (ESD) protection structure and a circuit using the same An electrostatic discharge (ESD) protection structure is disclosed. The ESD protection structure includes an active device. The active device includes a plurality of drains. Each of the drains has a contact row and at least one body contact row. The at least one bod... | 07/22/2008 |
| 7402868 | System and method for protecting semiconductor devices A semiconductor memory device includes a group of word lines and a structure that is configured to dissipate current from the group of word lines during fabrication of the semiconductor memory device. ... | 07/22/2008 |
| 7391069 | Semiconductor device and manufacturing method thereof In a conventional semiconductor device, for example, a MOS transistor, there is a problem that a parasitic transistor is prone to be operated due to an impurity concentration in a back gate region and a shape of diffusion thereof. In a semiconductor device of the pr... | 06/24/2008 |
| 7385253 | Device for electrostatic discharge protection and circuit thereof Disclosed herein are a device for electrostatic protection and circuit thereof. According to the present invention, a device for electrostatic discharge protection comprises first to third wells formed on a semiconductor substrate, a first device, which includes a w... | 06/10/2008 |
| 7372681 | Electrostatic discharge (ESD) protection device with simultaneous and distributed self-biasing for multi-finger turn-on An electrostatic discharge (ESD) protection circuit for a semiconductor integrated circuit (IC) that protects core circuitry of the IC during normal operations, and shunts ESD events during non-powered mode of the IC. The ESD protection circuitry includes a multi-fi... | 05/13/2008 |
| 7361957 | Device for electrostatic discharge protection and method of manufacturing the same The present invention relates to a device for electrostatic discharge protection (ESD). According to an embodiment of the present invention, a device for electrostatic discharge protection includes a semiconductor substrate, a plurality of field oxide films formed i... | 04/22/2008 |
| 7355250 | Electrostatic discharge device with controllable holding current An electrostatic discharge (ESD) device with a parasitic silicon controlled rectifier (SCR) structure and controllable holding current is provided. A first distance is kept between a first N+ doped region and a first P+ doped region, and a second distance is kept be... | 04/08/2008 |
| 7352031 | Electrostatic-breakdown-preventive and protective circuit for semiconductor-device A compact electrostatic-breakdown-preventive and protective circuit for a semiconductor-device capable of performing high-speed operations includes first and second protective transistors. The distance from a contact hole for connecting an impurity diffusion layer s... | 04/01/2008 |
| 7342276 | Method and apparatus utilizing monocrystalline insulator A semiconductor device, including: a semiconductor material; a conductive element; and a substantially monocrystalline insulator disposed between the semiconductor material and the conductive eleme... | 03/11/2008 |
| 7342282 | Compact SCR device and method for integrated circuits A semiconductor device and method for electrostatic discharge protection. The semiconductor device includes a first semiconductor controlled rectifier and a second semiconductor controlled rectifier. The first semiconductor controlled rectifier includes a first semi... | 03/11/2008 |
| 7335954 | Electrostatic discharge protection device An electrostatic discharge (ESD) protection device includes a first-type substrate, a second-type well formed in the substrate and a first-type well formed in the substrate. The second-type well includes a second-type+ region formed between first and second first-ty... | 02/26/2008 |
| 7327541 | Operation of dual-directional electrostatic discharge protection device A two-terminal ESD protection structure formed by an arrangement of five adjacent semiconductor regions (112, 114, 116, 118, and 120) of alternating conductivity type provides protection against both positive and negative ESD voltages. The middle semic... | 02/05/2008 |
| 7323752 | ESD protection circuit with floating diffusion regions This invention discloses an electrostatic discharge (ESD) protection circuit that comprises a substrate of a predetermined type, at least one MOS transistor being coupled to a pad of an integrated circuit for dissipating an ESD current from the pad during an ESD eve... | 01/29/2008 |
| 7323753 | MOS transistor circuit and voltage-boosting booster circuit To an output of an NMOS having one end connected to a power source, a capacitor and a PMOS are connected. A capacitor is connected to the output of the PMOS. The NMOS and the PMOS are turned on alternately. A pulse is applied to other end of the capacitor which is c... | 01/29/2008 |
| 7317633 | Protection of NROM devices from charge damage A method for protecting NROM devices from charge damage during process steps, the method including providing X-decoder structure for word line connections, wherein each word line is connected to a pair of transistors, a PMOS transistor and an NMOS transistor the PMO... | 01/08/2008 |
| 7298008 | Electrostatic discharge protection device and method of fabricating same Disclosed are a silicon control rectifier, a method of making the silicon control rectifier and the use of the silicon control rectifier as an electrostatic discharge protection device of an integrated circuit. The silicon control rectifier includes a silicon body f... | 11/20/2007 |
| 7294976 | Split power supply subsystem with isolated voltage supplies to satisfy a predetermined power limit A power subsystem including a mechanism for satisfying a predetermined power limit in a computer system. The power subsystem may include a split power supply and a voltage regulator. The split power supply may include at least a first voltage supply line and a secon... | 11/13/2007 |
| 7294935 | Integrated circuits protected against reverse engineering and method for fabricating the same using an apparent metal contact line terminating on field oxide Semiconducting devices, including integrated circuits, protected from reverse engineering comprising metal traces leading to field oxide. Metallization usually leads to the gate, source or drain areas of the circuit, but not to the insulating field oxide, thus misle... | 11/13/2007 |
| 7294892 | Multi-transistor layout capable of saving area A multi-transistor layout capable of saving area includes a substrate; a common drain comprising four sides formed over the substrate; four gates formed over the four sides of the common drain; and four sources formed over outer sides of the four gates corresponding... | 11/13/2007 |
