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| Number | Title | Issue Date |
| 8188545 | Integrated circuit device and electronic instrument A semiconductor integrated circuit includes N pad rows in which pads are respectively arranged, and electrostatic discharge protection elements disposed in a lower layer of the N pad rows and connected with each pad in the N pad rows. The electrostatic discharge pro... | 05/29/2012 |
| 8188544 | Integrated circuit device and electronic instrument An integrated circuit device includes a pad PDx and an electrostatic discharge protection element ESDx formed in a rectangular region and electrically connected with the pad PDx. The pad PDx is disposed in an upper layer of the electrostatic discharge protection ele... | 05/29/2012 |
| 8178925 | Semiconductor diode structure operation method A semiconductor structure operation method. The method includes providing a semiconductor structure. The semiconductor structure includes first, second, third, and fourth doped semiconductor regions. The second doped semiconductor region is in direct physical contac... | 05/15/2012 |
| 8174076 | Method for manufacturing electronic devices integrated in a semiconductor substrate and corresponding devices A method manufactures a vertical power MOS transistor on a semiconductor substrate comprising a first superficial semiconductor layer of a first conductivity type, comprising: forming trench regions in the first semiconductor layer, filling in said trench regions wi... | 05/08/2012 |
| 8174077 | High-voltage variable breakdown voltage (BV) diode for electrostatic discharge (ESD) applications Formation of an electrostatic discharge (ESD) protection device having a desired breakdown voltage (BV) is disclosed. The breakdown voltage (BV) of the device can be set, at least in part, by varying the degree to which a surface junction between two doped areas is ... | 05/08/2012 |
| 8159032 | Electronic device comprising an ESD device The electronic device comprises an ESD device (20) for protection against electrostatic discharge and provided with suitable protection elements (22) in combination with an integrated circuit (10). The integrated circuit (10) is particula... | 04/17/2012 |
| 8159033 | ESD protection device and manufacturing method thereof A junction forming region is formed between a drain region of a MOS structure and a device isolation region which surrounds the MOS structure and is in contact with the drain region, to form a PN junction together with the drain region. As a consequence, it is possi... | 04/17/2012 |
| 8148782 | Semiconductor device with ESD protection function and ESD protection circuit A semiconductor device with an ESD protection function has an SOI substrate, first to fourth diffusion layers, and a gate. The SOI substrate has a semiconductor layer on an insulation layer. The first diffusion layer is of a first conductivity type and is formed on ... | 04/03/2012 |
| 8148781 | Method and structures of monolithically integrated ESD suppression device This present invention relates in general to protection of integrated circuit chips, and more particularly, to a micromachined suppression device for protecting integrated circuit chips from electrostatic discharges. The proposed ESD suppression device consists of c... | 04/03/2012 |
| 8143672 | Semiconductor device including a metal layer having a first pattern and a second pattern which together form a web structure, thereby providing improved electrostatic discharge protection A semiconductor device includes a diode region having a plurality of protection diodes and a pad region overlapped with an upper part of the diode region. The pad region having a pad installed corresponding to an external connection terminal. The semiconductor devic... | 03/27/2012 |
| 8143673 | Circuit with electrostatic discharge protection A circuit with electrostatic discharge protection is described. The circuit includes an output driver transistor with an extended drain contact region. The circuit also includes a distinct device configured to provide electrostatic discharge protection for the outpu... | 03/27/2012 |
| 8138549 | System for displaying images A system for displaying images is disclosed. A display panel comprises a first substrate and a second substrate with a liquid crystal layer interposed therebetween. A sealant is interposed between the first substrate and a second substrate for sealing the liquid cry... | 03/20/2012 |
| 8138550 | Method of manufacturing a semiconductor device and a semiconductor device A method of manufacturing a semiconductor device, has forming a gate insulating film over a surface of a substrate, eliminating a portion of the gate insulating film in a region, forming a gate electrode over the gate insulating film and a drain electrode on the reg... | 03/20/2012 |
| 8134210 | Master, pixel array substrate, electro-optical device and methods of manufacturing the same A master having a substrate including displaying units and an ESD protection structure including an adjacent first region and a second region is provided. The displaying units have a predetermined-cutting region therebetween. Each displaying unit includes a peripher... | 03/13/2012 |
| 8134211 | Triggered silicon controlled rectifier for RF ESD protection An ESD protection circuit has a polysilicon bounded SCR connected between a signal input/output interface contact of the integrated circuit and a power supply connection of the integrated circuit and a biasing circuit. The biasing circuit is connected to the polysil... | 03/13/2012 |
| 8129788 | Capacitor triggered silicon controlled rectifier A protection circuit and method are provided for protecting semiconductor devices from electrostatic discharge (ESD). Generally, the ESD protection circuit includes a silicon controlled rectifier (SCR) formed in a substrate and configured to transfer charge from a p... | 03/06/2012 |
| RE43215 | ESD protection design with turn-on restraining method and structures The present invention is directed to an electrostatic discharge (ESD) device with an improved ESD robustness for protecting output buffers in I/O cell libraries. The ESD device according to the present invention uses a novel I/O cell layout structure for implementin... | 02/28/2012 |
| 8120112 | Method and apparatus for improving triggering uniformity of snapback electrostatic discharge protection devices An electrostatic discharge (ESD) protection circuit includes a first array of transistors, having source and drain doped with a first type of material, arranged in parallel in a first block, and a second array of transistors, having source and drain doped with the f... | 02/21/2012 |
| 8110875 | Structure for charge dissipation during fabrication of integrated circuits and isolation thereof A structure for dissipating charge during fabrication of an integrated circuit. The structure includes: a substrate contact in a semiconductor substrate; one or more wiring levels over the substrate; one or more electrically conductive charge dissipation structures ... | 02/07/2012 |
| 8106460 | Insulated gate semiconductor device A protection diode group includes multiple protection diodes connected to each other in parallel. A total junction area average of the protection diode group is set to a value large enough to guarantee a desired electrostatic discharge tolerance. By setting the tota... | 01/31/2012 |
| 8106461 | Apparatus for NBTI prediction An apparatus comprises a circuit for measuring a gate leakage current of a plurality of transistors. A circuit is provided to apply heat to gates of the plurality of transistors. A circuit is provided to apply a single stress bias voltage to the plurality of transis... | 01/31/2012 |
| 8102001 | Initial-on SCR device for on-chip ESD protection A semiconductor device for electrostatic discharge (ESD) protection includes a silicon controlled rectifier (SCR) including a semiconductor substrate, a first well formed in the substrate, a second well formed in the substrate, a first p-type region formed in the fi... | 01/24/2012 |
| 8097920 | Semiconductor integrated circuit comprising electro static discharge protection element An electro static discharge protection element being formed by a diode including a well region of a first conductivity type on a surface of a semiconductor substrate, and a first diffusion layer of a second conductivity type in the well region. The first diffusion l... | 01/17/2012 |
| 8084821 | Integrated circuit including a power MOS transistor An integrated circuit includes a first transistor having a first gate and a first source and a second transistor having a second gate and a second source. The integrated circuit includes a first source contact adjacent the second transistor and coupled to the first ... | 12/27/2011 |
| 8086979 | Method for designing and manufacturing a PMOS device with drain junction breakdown point located for reduced drain breakdown voltage walk-in A PMOS device can be designed and manufactured in accordance with the invention to locate its drain junction breakdown point and maximum impact ionization point to reduce or eliminate drain breakdown voltage walk-in. In some embodiments, the drain junction breakdown... | 12/27/2011 |
| 8080851 | Deep trench electrostatic discharge (ESD) protect diode for silicon-on-insulator (SOI) devices A semiconductor structure is disclosed. The semiconductor structure includes a bulk substrate of a first polarity type, a buried insulator layer disposed on the bulk substrate, an active semiconductor layer disposed on top of the buried insulator layer including a s... | 12/20/2011 |
| 8076728 | Integrated circuit arrangements with ESD-resistant capacitor and corresponding method of production A circuit arrangement including a capacitor in an n-type well is disclosed. A specific polarization of the capacitor ensures that a depletion zone arises in the well and the capacitor has a high ESD strength. An optionally present auxiliary doping layer ensures a hi... | 12/13/2011 |
| 8072030 | Semiconductor device A semiconductor device, which is connected to a protected device and protects a protected device, includes a semiconductor layer provided on an insulating film; a plurality of source layers which is formed in the semiconductor layer and extends in a first direction;... | 12/06/2011 |
| 8044466 | ESD protection device in high voltage and manufacturing method for the same An ESD protection device comprises a substrate of a first conductive type; a transistor formed in the substrate having an input terminal of the first conductive type, a control terminal of a second conductive type, and a ground terminal of the first conductive type;... | 10/25/2011 |
| 8039899 | Electrostatic discharge protection device An electrostatic discharge protection device includes a first well comprising a MOS transistor; a second well comprising a first impurity region to which a first voltage is applied, and a second impurity region connected to an input/output pad, the second well being... | 10/18/2011 |
| 8035162 | System and method for ESD protection An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programmable attenuation and a programmable gain low noise amplifier. Frequency conversion cir... | 10/11/2011 |
| 8022479 | Semiconductor apparatus A semiconductor apparatus includes a semiconductor substrate, an insulating film provided on the semiconductor substrate, and a semiconductor film provided on the insulating film. The semiconductor substrate includes a region of a first current path including at lea... | 09/20/2011 |
| 8018000 | Electrostatic discharge protection pattern for high voltage applications Electrostatic discharge (ESD) protection in high voltage semiconductor devices is disclosed that provides enhanced current isolation between transistor drains or sources by creating an isolation island surrounding the drains or sources. This isolation island can be ... | 09/13/2011 |
| 8017999 | Semiconductor device An output side of a driver output circuit of an LCD driver includes a first protective element having an n-type semiconductor region and a p-type semiconductor region formed in the n-type semiconductor region, and a second protective element having a p-type semicond... | 09/13/2011 |
| 8013393 | Electrostatic discharge protection devices A method for fabricating a semiconductor device is provided. According to this method, a first gate electrode and a second gate electrode are formed overlying a first portion of a silicon substrate, and ions of a first conductivity-type are implanted into a second p... | 09/06/2011 |
| 8008723 | Semiconductor device including a plurality of diffusion layers and diffusion resistance layer Aimed at reducing the area of a protective circuit in a semiconductor device provided therewith, a semiconductor device of the present invention has a first-conductivity-type well, a plurality of first diffusion layers formed in the well, a plurality of second diffu... | 08/30/2011 |
| 8004041 | Semiconductor device for surge protection A semiconductor device for surge protection having high surge resistance is provided. A semiconductor substrate (10) included in the semiconductor device for surge protection according to the present invention includes a high concentration first conductivity ... | 08/23/2011 |
| 7994577 | ESD protection structures on SOI substrates An electrostatic discharge (ESD) protection circuit includes a buried oxide layer; a semiconductor layer on the buried oxide layer; and a first and a second MOS device. The first MOS device includes a first gate over the semiconductor layer; a first well region havi... | 08/09/2011 |
| 7994578 | ESD protection for bipolar-CMOS-DMOS integrated circuit devices An Electro-Static Discharge (ESD) protection device is formed in an isolated region of a semiconductor substrate. The ESD protection device may be in the form of a MOS or bipolar transistor or a diode. The isolation structure may include a deep implanted floor layer... | 08/09/2011 |
| 7989894 | Fusion bonding process and structure for fabricating silicon-on-insulation (SOI) semiconductor devices A method of fabricating a semiconductor-on-insulator device including: providing a first semiconductor wafer having an about 500 angstrom thick oxide layer thereover; etching the first semiconductor wafer to raise a pattern therein; doping the raised pattern of the ... | 08/02/2011 |
