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| Number | Title | Issue Date |
| 8183636 | Static randon access memory cell One or more embodiments relate to a static random access memory cell comprising: a first inverter including a first n-channel pull-down transistor coupled between a first node and a ground voltage; a second inverter including a second n-channel pull-down transistor ... | 05/22/2012 |
| 8183635 | Semiconductor device A technique to be applied to a semiconductor device for achieving low power consumption by improving a shape at a boundary portion of a shallow trench and an SOI layer of an SOI substrate. A position (SOI edge) at which a main surface of a silicon substrate and a li... | 05/22/2012 |
| 8178924 | Semiconductor device having floating body element and bulk body element A semiconductor device having a floating body element and a bulk body element and a manufacturing method thereof are provided. The semiconductor device includes a substrate having a bulk body element region and floating body element regions. An isolation region defi... | 05/15/2012 |
| 8169025 | Strained CMOS device, circuit and method of fabrication A semiconductor device and fabrication method include a strained semiconductor layer having a strain in one axis. A long fin and a short fin are formed in the semiconductor layer such that the long fin has a strained length along the one axis. An n-type transistor i... | 05/01/2012 |
| 8169026 | Stress-induced CMOS device A semiconductor device including: a silicon dioxide layer; an n-type field effect transistor (NFET) including at least one recessed source/drain trench and located over a portion of the silicon dioxide layer; a p-type field effect transistor (PFET) including at leas... | 05/01/2012 |
| 8154082 | Semiconductor device and manufacturing method thereof A semiconductor device includes an NMISFET region. The NMISFET region includes a Ge nano wire having a triangular cross section along a direction perpendicular to a channel current direction, wherein two of surfaces that define the triangular cross section of the Ge... | 04/10/2012 |
| 8120110 | Semiconductor structure including a high performance FET and a high voltage FET on a SOI substrate A first field effect transistor includes a gate dielectric and a gate electrode located over a first portion of a top semiconductor layer in a semiconductor-on-insulator (SOI) substrate. A second field effect transistor includes a portion of a buried insulator layer... | 02/21/2012 |
| 8110874 | Hybrid substrates and method of manufacture A hybrid substrate circuit on a common substrate is disclosed. A first circuit formed in a first semiconductor material is isolated via a buried oxide layer from a second circuit formed in a second semiconductor material. The first and second circuits may include CM... | 02/07/2012 |
| 8106458 | SOI CMOS circuits with substrate bias The present invention relates to methods and devices for reducing the threshold voltage difference between an n-type field effect transistor (n-FET) and a p-type field effect transistor (p-FET) in a complementary metal-oxide-semiconductor (CMOS) circuit located on a... | 01/31/2012 |
| 8044464 | Semiconductor device An object is to realize high performance and low power consumption in a semiconductor device having an SOI structure. In addition, another object is to provide a semiconductor device having a high performance semiconductor element which is more highly integrated. A ... | 10/25/2011 |
| 8013392 | High mobility CMOS circuits Semiconductor structure formed on a substrate and process of forming the semiconductor. The semiconductor includes a plurality of field effect transistors having a first portion of field effect transistors (FETS) and a second portion of field effect transistors. A f... | 09/06/2011 |
| 7999323 | Using metal/metal nitride bilayers as gate electrodes in self-aligned aggressively scaled CMOS devices The present invention is directed to CMOS structures that include at least one nMOS device located on one region of a semiconductor substrate; and at least one pMOS device located on another region of the semiconductor substrate. In accordance with the present inven... | 08/16/2011 |
| 7989893 | SOI body contact using E-DRAM technology A semiconductor structure is disclosed. The semiconductor structure includes an active semiconductor layer, a semiconductor device having a gate disposed on top of the active semiconductor layer, and source and drain regions and a body/channel region disposed within... | 08/02/2011 |
| 7986008 | SOI semiconductor components and methods for their fabrication SOI semiconductor components and methods for their fabrication are provided wherein the SOI semiconductor components include an MOS transistor in the supporting semiconductor substrate. In accordance with one embodiment the component comprises a semiconductor on ins... | 07/26/2011 |
| 7939891 | Semiconductor device having MISFETs and manufacturing method thereof A semiconductor device includes a dielectric film and gate electrode that are stacked on a substrate, sidewalls formed to cover the side surfaces of the electrode and dielectric film, and SiGe films formed to sandwich the sidewalls, electrode and dielectric film, fi... | 05/10/2011 |
| 7910997 | Method for manufacturing CMOS circuits and CMOS circuits manufactured thereof A method of manufacturing transistors of a first and second type on a substrate includes producing doped semiconductor areas with a first conductivity type in eventual contact areas of a first type of transistors, depositing a first intrinsic semiconductor layer ove... | 03/22/2011 |
| 7834399 | Dual stress memorization technique for CMOS application A stress-transmitting dielectric layer is formed on the at least one PFET and the at least one NFET. A tensile stress generating film, such as a silicon nitride, is formed on the at least one NFET by blanket deposition and patterning. A compressive stress generating... | 11/16/2010 |
| 7829949 | High-K dielectric metal gate device structure A metal gate/high-k dielectric semiconductor device provides an NMOS gate structure and a PMOS gate structure formed on a semiconductor substrate. The NMOS gate structure includes a high-k gate dielectric treated with a dopant impurity such as La and the high-k gate... | 11/09/2010 |
| 7825472 | Semiconductor device having a plurality of stacked transistors and method of fabricating the same A semiconductor device according to example embodiments may have a plurality of stacked transistors. The semiconductor device may have a lower insulating layer formed on a semiconductor substrate and an upper channel body pattern formed on the lower insulating layer... | 11/02/2010 |
| 7804134 | MOSFET on SOI device A MOSFET on SOI device includes an upper region having at least one first MOSFET type semi-conductor device formed on a first semi-conductor layer stacked on a first dielectric layer, a first conductive layer and a first portion of a second semi-conductor layer. A l... | 09/28/2010 |
| 7800179 | High speed, low power consumption, isolated analog CMOS unit A semiconductor device 100 has N-well regions 18 holding PMOS devices 110, 112 and P-type regions 14 holding NMOS devices 114, 116. Devices 110 and 114 have high thresholds and devices 112 and 116 have l... | 09/21/2010 |
| 7795682 | Semiconductor device and method manufacturing semiconductor device The disclosure concerns a method of manufacturing a semiconductor device including forming a plurality of fins made of a semiconductor material on an insulating layer; forming a gate insulating film on side surfaces of the plurality of fins; and forming a gate elect... | 09/14/2010 |
| 7791141 | Field-enhanced programmable resistance memory cell Provides a field-enhanced programmable resistance memory cell. In an example embodiment, a resistor includes a resistance structure between a first electrode and a second electrode. The resistance structure includes an insulating dielectric material. The second elec... | 09/07/2010 |
| 7781840 | Semiconductor device structure Two different transistors types are made on different crystal orientations in which both are formed on SOI. A substrate has an underlying semiconductor layer of one of the crystal orientations and an overlying layer of the other crystal orientation. The underlying l... | 08/24/2010 |
| 7755141 | Complementary MISFET formed in a linear body Integrated circuits such as semiconductor memories, image sensors, PLA's, and the like have been formed on rigid, planar substrates such as silicon substrates. This has resulted in shapes without flexibility and limited applicabilities. Further, since multiple circu... | 07/13/2010 |
| 7741679 | Semiconductor device, method of manufacturing same and method of designing same A partial oxide film with well regions formed therebeneath isolates transistor formation regions in an SOI layer from each other. A p-type well region is formed beneath part of the partial oxide film which isolates NMOS transistors from each other, and an n-type wel... | 06/22/2010 |
| 7728384 | Magnetic random access memory using single crystal self-aligned diode A magnetic random access memory (MRAM) cell comprises a MRAM device and a single crystal self-aligned diode. The MRAM device and the single crystal self-aligned diode are connected through a contact. Only one metal line is positioned above the MRAM device of the MRA... | 06/01/2010 |
| 7719059 | Fin field effect transistor arrangement and method for producing a fin field effect transistor arrangement A fin field effect transistor arrangement comprises a substrate and a first fin field effect transistor on and/or in the substrate. The first fin field effect transistor includes a fin in which a channel region is formed between a first source/drain region and a sec... | 05/18/2010 |
| 7705402 | Semiconductor device including a nitride containing film to generate stress for improving current driving capacity of a field effect transistor A semiconductor device includes an n channel conductivity type FET having a channel formation region formed in a first region on a main surface of a semiconductor substrate and a p channel conductivity type FET having a channel formation region formed in a second re... | 04/27/2010 |
| 7701011 | Printed dopant layers An electronic device, including a substrate, a plurality of first semiconductor islands on the substrate, a plurality of second semiconductor islands on the substrate, a first dielectric film on the first subset of the semiconductor islands, second dielectric film o... | 04/20/2010 |
| 7675115 | Semiconductor device and method for manufacturing the same A semiconductor device includes a Si substrate, an insulating film formed on onepart of the Si substrate, a bulk Si region grown on other part of the Si substrate other than the insulating film, Si1-xGex (0 | 03/09/2010 |
| 7659583 | Ultrathin SOI CMOS devices employing differential STI liners An oxynitride pad layer and a masking layer are formed on an ultrathin semiconductor-on-insulator substrate containing a top semiconductor layer comprising silicon. A first portion of a shallow trench is patterned in a top semiconductor layer by lithographic masking... | 02/09/2010 |
| 7606098 | Semiconductor memory array architecture with grouped memory cells, and method of controlling same An integrated circuit device (e.g., a logic device or a memory device) having a memory cell array including a plurality of word lines (e.g., first and second word lines) and a plurality of word line segments (e.g., first and second word line segments) wherein each w... | 10/20/2009 |
| 7589383 | Thin film semiconductor device and method of manufacturing the same A thin film semiconductor device has: a substrate; a low-voltage thin film transistor formed on the substrate and having a first gate insulating film; and a high-voltage thin film transistor formed on the substrate and having a second gate insulating film whose thic... | 09/15/2009 |
| 7582935 | Methods for manufacturing SOI substrate using wafer bonding and complementary high voltage bipolar transistor using the SOI substrate A method of manufacturing an SOI substrate for semiconductor devices is described. The method includes forming a low density impurity region in a first semiconductor substrate and a high density impurity region in the low density impurity region, forming a trench su... | 09/01/2009 |
| 7576395 | Dual gate stack CMOS structure with different dielectrics Integrated circuit devices include a semiconductor substrate having a first doped region and a second doped region having a different doping type than the first doped region. A gate electrode structure on the semiconductor substrate extends between the first and sec... | 08/18/2009 |
| 7531878 | Semiconductor MIS transistor formed on SOI semiconductor substrate There is provided a semiconductor device which is formed on a semiconductor substrate and allows effective use of the feature of the semiconductor substrate, and there is also provided a method of manufacturing the same. An N-channel MOS transistor including a P-typ... | 05/12/2009 |
| 7498637 | Semiconductor memory A SRAM memory is composed of FD-SOI transistors, and performance of the memory cell is improved by controlling an electric potential of a layer under a buried oxide film of a SOI transistor constituting a driver transistor. Performance of the SRAM circuit in the low... | 03/03/2009 |
| 7485929 | Semiconductor-on-insulator (SOI) strained active areas Differentially strained active regions for forming strained channel semiconductor devices and a method of forming the same, the method including providing a semiconductor substrate comprising a lower semiconductor region, an insulator region overlying the lower semi... | 02/03/2009 |
| 7482658 | Semiconductor device and method of manufacturing the same An isolation insulating film (5) of partial-trench type is selectively formed in an upper surface of a silicon layer (4). A power supply line (21) is formed above the isolation insulating film (5). Below the power supply line (21),... | 01/27/2009 |
