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| Number | Title | Issue Date |
| 8164144 | Semiconductor device and manufacturing method thereof A semiconductor device includes a semiconductor layer on an insulating layer, and a first partially depleted transistor and a first diode in the semiconductor layer. The first transistor has a first gate electrode above the semiconductor layer via an insulating film... | 04/24/2012 |
| 8106457 | Silicon-on-insulator based radiation detection device and method Structures and a method for detecting ionizing radiation using silicon-on-insulator (SOI) technology are disclosed. In one embodiment, the invention includes a substrate having a buried insulator layer formed over the substrate and an active layer formed over the bu... | 01/31/2012 |
| 8026551 | Source follower circuit or bootstrap circuit, driver circuit comprising such circuit, and display device comprising such driver circuit In the case of using an analog buffer circuit, an input voltage is required to be added a voltage equal to a voltage between the gate and source of a polycrystalline silicon TFT; therefore, a power supply voltage is increased, thus a power consumption is increased w... | 09/27/2011 |
| 7943997 | Fully-depleted low-body doping field effect transistor (FET) with reverse short channel effects (SCE) induced by self-aligned edge back-gate(s) Disclosed are embodiments of a field effect transistor (FET) and, more particularly, a fully-depleted, thin-body (FDTB) FET that allows for scaling with minimal short channel effects, such as drain induced barrier lowering (DIBL) and saturation threshold voltage (Vt... | 05/17/2011 |
| 7928509 | Integrated JFET and schottky diode The present invention discloses an integrated junction field effect transistor (JFET) and Schottky diode, comprising a depletion mode JFET which includes a source, a drain and a gate, wherein the drain is not provided with an ohmic contact such that it forms a Schot... | 04/19/2011 |
| 7847354 | Semiconductor device with multiple transistors formed in a partially depleted semiconductor-on-insulator substrate A semiconductor device comprises a partially depleted semiconductor-on-insulator structure having both a three terminal JFET and a four terminal JFET constructed thereon. The four terminal JFET comprises a source region, a drain region, a channel region, a front gat... | 12/07/2010 |
| 7847353 | Multi-thickness semiconductor with fully depleted devices and photonic integration Techniques are disclosed that facilitate fabrication of semiconductors including structures and devices of varying thickness. One embodiment provides a method for semiconductor device fabrication that includes thinning a region of a semiconductor wafer upon which th... | 12/07/2010 |
| 7795680 | Integrated circuit system employing selective epitaxial growth technology An integrated circuit system that includes: providing a substrate; depositing a dielectric on the substrate; depositing an isolation dielectric on the dielectric; forming a trench through the isolation dielectric and the dielectric to expose the substrate; depositin... | 09/14/2010 |
| 7772647 | Structure and design structure having isolated back gates for fully depleted SOI devices Methods, structure and design structure having isolated back gates for fully depleted semiconductor-on-insulator (FDSOI) devices are presented. In one embodiment, a method may include providing a FDSOI substrate having a SOI layer over a buried insulator over a firs... | 08/10/2010 |
| 7772646 | Method of manufacturing a semiconductor device and such a semiconductor device There is a method of manufacturing a semiconductor device with a semiconductor body comprising a semiconductor substrate and a semiconductor region which are separated from each other with an electrically insulating layer which includes a first and a second sub-laye... | 08/10/2010 |
| 7745879 | Method of fabricating high voltage fully depleted SOI transistor and structure thereof A method of fabricating a high voltage fully depleted silicon-on-insulator (FD SOI) transistor, the FD SOI transistor having a structure including a region within a body on which a gate structure is disposed. The region includes a channel separating the source regio... | 06/29/2010 |
| 7719058 | Mixed-signal semiconductor platform incorporating fully-depleted castellated-gate MOSFET device and method of manufacture thereof A Mixed-Signal Semiconductor Platform Incorporating Castellated-Gate MOSFET device(s) capable of Fully-Depleted operation is disclosed along with a method of making the same. The composite device/technology platform has robust I/O applications and includes a startin... | 05/18/2010 |
| 7701009 | Source follower circuit or bootstrap circuit, driver circuit comprising such circuit, and display device comprising such driver circuit In the case of using an analog buffer circuit, an input voltage is required to be added a voltage equal to a voltage between the gate and source of a polycrystalline silicon TFT; therefore, a power supply voltage is increased, thus a power consumption is increased w... | 04/20/2010 |
| 7692244 | Electronically scannable multiplexing device An electronically scannable multiplexing device is capable of addressing multiple bits within a volatile or non-volatile memory cell. The multiplexing device generates an electronically scannable conducting channel with two oppositely formed depletion regions. The d... | 04/06/2010 |
| 7514748 | Semiconductor device A semiconductor device such as a DRAM memory device is disclosed. A substrate (12) of semiconductor material is provided with energy band modifying means in the form of a box region (38) and is covered by an insulating layer (14). A semiconducto... | 04/07/2009 |
| 7459752 | Ultra thin body fully-depleted SOI MOSFETs Ultra thin body fully-depleted silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect-transistors (MOSFETs) in which the SOI thickness changes with gate-length variations thereby minimizing the threshold voltage variations that are typically caused by SOI... | 12/02/2008 |
| 7439178 | Technique for stable processing of thin/fragile substrates A semiconductor on insulator (SOI) wafer includes a semiconductor substrate having first and second main surfaces opposite to each other. A dielectric layer is disposed on at least a portion of the first main surface of the semiconductor substrate. A device layer ha... | 10/21/2008 |
| 7429773 | Semiconductor apparatus and MIS logic circuit A configuration is adopted including an NchMOS transistor (1) equipped with an insulating isolation layer (4) providing insulation and isolation using an SOI structure, and a capacitor formed using an insulating film, with a silicon substrate (B) being... | 09/30/2008 |
| 7423324 | Double-gate MOS transistor, double-gate CMOS transistor, and method for manufacturing the same In a double-gate MOS transistor, a substrate, an insulating layer, and a semiconductor layer are formed or laminated in that order, an opening extending to the insulating layer is formed in the semiconductor layer while leaving an island-shaped region, the island-sh... | 09/09/2008 |
| 7388258 | Sectional field effect devices A field effect device is disclosed which has a body formed of a crystalline semiconductor material and has at least one vertically oriented section and at least one horizontally oriented section. The device is produced in SOI technology by fabricating first a format... | 06/17/2008 |
| 7382023 | Fully depleted SOI multiple threshold voltage application An integrated circuit comprises a substrate and a buried dielectric formed in the substrate. The buried dielectric has a first thickness in a first region, a second buried dielectric thickness in a second region, and a step between the first and second regions. A se... | 06/03/2008 |
| 7378710 | FinFET SRAM cell using inverted FinFET thin film transistors An integrated circuit, such as a SRAM cell (130), including an inverted FinFET transistor (P2) and a FinFET transistor (N3). The inverted FinFET transistor includes a first gate region (108) formed by semiconductor structure (100) ... | 05/27/2008 |
| 7368392 | Method of fabricating a gate structure of a field effect transistor having a metal-containing gate electrode A method of etching metals and/or metal-containing compounds using a plasma comprising a bromine-containing gas. In one embodiment, the method is used during fabrication of a gate structure of a field effect transistor having a titanium nitride gate electrode, an ul... | 05/06/2008 |
| 7368788 | SRAM cells having inverters and access transistors therein with vertical fin-shaped active regions Complementary metal oxide semiconductor (CMOS) static random access memory (SRAM) cells include at least a first inverter formed in a fin-shaped pattern of stacked semiconductor regions of opposite conductivity type. In some of these embodiments, the first inverter ... | 05/06/2008 |
| 7365401 | Dual-plane complementary metal oxide semiconductor Embodiments herein present a device, method, etc. for a dual-plane complementary metal oxide semiconductor. The device comprises a fin-type transistor on a bulk silicon substrate. The fin-type transistor comprises outer fin regions and a center semiconductor fin reg... | 04/29/2008 |
| 7358131 | Methods of forming SRAM constructions The invention includes SRAM constructions comprising at least one transistor device having an active region extending into a crystalline layer comprising Si/Ge. A majority of the active region within the crystalline layer is within a single crystal of the crystallin... | 04/15/2008 |
| 7358571 | Isolation spacer for thin SOI devices A semiconductor device comprises a semiconductor mesa overlying a dielectric layer, a gate stack formed overlying the semiconductor mesa, and an isolation spacer formed surrounding the semiconductor mesa and filling any undercut region at edges of the semiconductor ... | 04/15/2008 |
| 7358569 | Semiconductor device with semiconductor layer having various thickness An SOI layer is provided in a buried oxide film and a source and a drain are provided on the upper surface of the SOI layer so that they are kept from contact with the buried oxide film. A depletion layer formed by the source, the drain, and the SOI layer extends to... | 04/15/2008 |
| 7355223 | Vertical junction field effect transistor having an epitaxial gate A vertical junction field effect transistor includes a trench formed in an epitaxial layer. The trench surrounds a channel region of the epitaxial layer. The channel region may have a graded or uniform dopant concentration profile. An epitaxial gate structure is for... | 04/08/2008 |
| 7355247 | Silicon on diamond-like carbon devices Embodiments of the invention provide substrate with an insulator layer on the substrate. The insulator layer may include diamond-like carbon. A device, such a tri-gate transistor may be formed on the diamond-like carbon layer. ... | 04/08/2008 |
| 7355249 | Silicon-on-insulator based radiation detection device and method Structures and a method for detecting ionizing radiation using silicon-on-insulator (SOI) technology are disclosed. In one embodiment, the invention includes a substrate having a buried insulator layer formed over the substrate and an active layer formed over the bu... | 04/08/2008 |
| 7348284 | Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow A non-planar tri-gate p-MOS transistor structure with a strained channel region and a non-planar tri-gate integrated strained complimentary metal-oxide-semiconductor (CMOS) structure are described. A relaxed Si1-x Gex layer is formed on the sil... | 03/25/2008 |
| 7335950 | Semiconductor device and method of making thereof To provide a thin film transistor having a low OFF characteristic and to provide P-channel type and N-channel type thin film transistors where a difference in characteristics of the P-channel type and the N-channel type thin film transistors is corrected, a region | 02/26/2008 |
| 7335934 | Integrated circuit device, and method of fabricating same There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to integrated circuit device including SOI logic transistors and SOI memory transistors, and method for fabricating such a device. In one embodiment, int... | 02/26/2008 |
| 7332776 | Semiconductor device A partial isolation insulating film provided between MOS transistors in an NMOS region and a PMOS region, respectively, has a structure in which a portion protruding upward from a main surface of an SOI layer is of greater thickness than a trench depth, namely, a po... | 02/19/2008 |
| 7329937 | Asymmetric field effect transistors (FETs) A semiconductor structure and a method for forming the same. The structure includes (a) a semiconductor channel region, (b) a semiconductor source block in direct physical contact with the semiconductor channel region; (c) a source contact region in direct physical ... | 02/12/2008 |
| 7315060 | Semiconductor storage device, manufacturing method therefor and portable electronic equipment A semiconductor storage device has a single gate electrode formed on a semiconductor substrate through a gate insulation film. First and second memory function bodies formed on both sides of the gate electrode. A P-type channel region is formed in a surface of the s... | 01/01/2008 |
| 7312515 | Semiconductor apparatus including a thin-metal-film resistor element and a method of manufacturing the same A semiconductor apparatus includes a wiring pattern, an insulating film, and a thin-metal-film resistor element. The insulating film is formed on the wiring pattern having connection holes vertically penetrating there-through to expose part of the wiring pattern at ... | 12/25/2007 |
| 7307318 | Semiconductor device A partial isolation insulating film provided between MOS transistors in an NMOS region and a PMOS region, respectively, has a structure in which a portion protruding upward from a main surface of an SOI layer is of greater thickness than a trench depth, namely, a po... | 12/11/2007 |
| 7288443 | Structures and methods for manufacturing p-type MOSFET with graded embedded silicon-germanium source-drain and/or extension P-type MOSFETs (PMOSFETs) are formed by encapsulating the gate with an insulator and depositing a germanium containing layer outside the sidewalls, then diffusing the germanium into the silicon-on-insulator layer or bulk silicon by annealing or by oxidizing to form ... | 10/30/2007 |
