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| Number | Title | Issue Date |
| 8426916 | Semiconductor integrated circuit devices having different thickness silicon-germanium layers Methods of fabricating semiconductor integrated circuit devices are provided. A substrate is provided with gate patterns formed on first and second regions. Spaces between gate patterns on the first region are narrower than spaces between gate patterns on the second... | 04/23/2013 |
| 8017997 | Vertical metal-insulator-metal (MIM) capacitor using gate stack, gate spacer and contact via A semiconductor structure including a vertical metal-insulator-metal capacitor, and a method for fabricating the semiconductor structure including the vertical metal-insulator-metal capacitor, each use structural components from a dummy metal oxide semiconductor fie... | 09/13/2011 |
| 7893492 | Nanowire mesh device and method of fabricating same A semiconductor structure is provided that includes a plurality of vertically stacked and vertically spaced apart semiconductor nanowires (e.g., a semiconductor nanowire mesh) located on a surface of a substrate. One end segment of each vertically stacked and vertic... | 02/22/2011 |
| 7560776 | Semiconductor device, electronic apparatus, method of manufacturing semiconductor device, and method of manufacturing electronic apparatus A semiconductor device includes first and second electrodes disposed apart from each other on a substrate, a gate electrode disposed so as to face the first and second electrodes and to cover at least part of each of the first and second electrodes, a semiconductor ... | 07/14/2009 |
| 7436026 | Semiconductor device comprising a superlattice channel vertically stepped above source and drain regions A semiconductor device may include a semiconductor substrate and at least one metal oxide semiconductor field-effect transistor (MOSFET). The at least one MOSFET may include spaced apart source and drain regions in the semiconductor substrate, and a superlattice cha... | 10/14/2008 |
| 7420241 | Semiconductor memory device and method of manufacturing the same A semiconductor memory device includes a memory cell which includes a first gate insulation film provided on the semiconductor substrate; a floating gate electrode provided on the first gate insulation film; a second gate insulation film provided on the floating gat... | 09/02/2008 |
| 7355245 | Structure for reducing overlap capacitance in field effect transistors A field effect transistor (FET) device includes a gate conductor formed over a semiconductor substrate, a source region having a source extension that overlaps and extends under the gate conductor, and a drain region having a drain extension that overlaps and extend... | 04/08/2008 |
| 7348675 | Microcircuit fabrication and interconnection Embodiments of methods in accordance with the present invention provide three-dimensional carbon nanotube (CNT) integrated circuits comprising layers of arrays of CNT's separated by dielectric layers with conductive traces formed within the dielectric layers to elec... | 03/25/2008 |
| 7348629 | Metal gated ultra short MOSFET devices MOSFET devices suitable for operation at gate lengths less than about 40 nm, and methods of their fabrication is being presented. The MOSFET devices include a ground plane formed of a monocrystalline Si based material. A Si based body layer is epitaxially disposed o... | 03/25/2008 |
| 7345341 | High voltage semiconductor devices and methods for fabricating the same High voltage semiconductor devices and methods for fabricating the same are provided. An exemplary embodiment of a semiconductor device capable of high-voltage operation, comprising a substrate comprising a first well formed therein. A gate stack is formed overlying... | 03/18/2008 |
| 7338883 | Process for transferring a layer of strained semiconductor material The invention relates to a process for producing an electronic structure that includes a thin layer of strained semiconductor material from a donor wafer. The donor wafer has a lattice parameter matching layer that includes an upper layer of a semiconductor material... | 03/04/2008 |
| 7332775 | Protruding spacers for self-aligned contacts A protruding spacer that protrudes above the top surface of a gate electrode structure provides enhanced resistance to exposure of the gate electrode during the etch process used to form self-aligned contacts. The protruding spacer may be formed using an amorphous c... | 02/19/2008 |
| 7329571 | Technique for providing multiple stress sources in NMOS and PMOS transistors By combining a plurality of stress inducing mechanisms in each of different types of transistors, a significant performance gain may be obtained, thereby providing enhanced flexibility in adjusting product specific characteristics. For this purpose, sidewall spacers... | 02/12/2008 |
| 7329567 | Vertical field effect transistors incorporating semiconducting nanotubes grown in a spacer-defined passage Vertical field effect transistors having a channel region defined by at least one semiconducting nanotube and methods for fabricating such vertical field effect transistors by chemical vapor deposition using a spacer-defined channel. Each nanotube is grown by chemic... | 02/12/2008 |
| 7323726 | Method and apparatus for coupling to a common line in an array A method and apparatus for coupling to a common line in an array. Gate structures of an integrated circuit are formed. Source and drain regions adjacent to the gate structures are implanted. A source contact from a metal Vss line to a source region is formed. Dopant... | 01/29/2008 |
| 7319252 | Methods for forming semiconductor wires and resulting devices Methods for forming a wire from silicon or other semiconductor material are disclosed. Also disclosed are various devices including such a semiconductor wire. According to one embodiment, a wire is spaced apart from an underlying substrate, and the wire extends betw... | 01/15/2008 |
| 7301191 | Fabricating carbon nanotube transistor devices During fabrication of single-walled carbon nanotube transistor devices, a porous template with numerous parallel pores is used to hold the single-walled carbon nanotubes. The porous template or porous structure may be anodized aluminum oxide or another material. A g... | 11/27/2007 |
| 7288817 | Reverse metal process for creating a metal silicide transistor gate structure The present invention teaches a method of forming a MOSFET transistor having a silicide gate which is not subject to problems produced by etching a metal containing layer when forming the gate stack structure. A gate stack is formed over a semiconductor substrate co... | 10/30/2007 |
| 7288814 | Selective post-doping of gate structures by means of selective oxide growth A method for doping a polysilicon gate conductor, without implanting the substrate in a manner that would effect source/drain formation is provided. The inventive method comprises forming at least one polysilicon gate region atop a substrate; forming oxide seed spac... | 10/30/2007 |
| 7253482 | Structure for reducing overlap capacitance in field effect transistors A field effect transistor (FET) device includes a gate conductor formed over a semiconductor substrate, a source region having a source extension that overlaps and extends under the gate conductor, and a drain region having a drain extension that overlaps and extend... | 08/07/2007 |
| 7235433 | Silicon-on-insulator semiconductor device with silicon layers having different crystal orientations and method of forming the silicon-on-insulator semiconductor device A semiconductor device comprising a substrate having a first crystal orientation and an insulating layer overlying the substrate is provided. A plurality of silicon layers are formed overlying the insulating layer. A first silicon layer comprises silicon having the ... | 06/26/2007 |
| 7233071 | Low-k dielectric layer based upon carbon nanostructures A low-k dielectric material for use in the manufacture of semiconductor devices, semiconductor structures using the low-k dielectric material, and methods of forming such dielectric materials and fabricating such structures. The low-k dielectric material comprises c... | 06/19/2007 |
| 7221021 | Method of forming high voltage devices with retrograde well A high voltage device with retrograde well is disclosed. The device comprises a substrate, a gate region formed on the substrate, and a retrograde well placed in the substrate next to the gate region, wherein the retrograde well reduces a dopant concentration on the... | 05/22/2007 |
| 7211961 | Thin film transistor circuit and display utilizing the same There is provided a method of easily forming thin film transistors having the same characteristics in fabricating a differential circuit or a current mirror circuit utilizing two thin film transistors made of a polycrystalline silicon semiconductor. Four each thin f... | 05/01/2007 |
| 7208361 | Replacement gate process for making a semiconductor device that includes a metal gate electrode A method for making a semiconductor device is described. That method comprises forming a polysilicon layer on a dielectric layer, which is formed on a substrate. The polysilicon layer is etched to generate a patterned polysilicon layer with an upper surface that is ... | 04/24/2007 |
| 7205609 | Methods of forming semiconductor devices including fin structures and related devices A method of forming a semiconductor device may include forming a fin structure extending from a substrate. The fin structure may include first and second source/drain regions and a channel region therebetween, and the first and second source/drain regions may extend... | 04/17/2007 |
| 7189623 | Semiconductor processing method and field effect transistor A method of forming a transistor gate includes forming a gate oxide layer over a semiconductive substrate. Chlorine is provided within the gate oxide layer. A gate is formed proximate the gate oxide layer. In another method, a gate and a gate oxide layer are formed ... | 03/13/2007 |
| 7176520 | Semiconductor device and a method of manufacturing the same To reduce the size and improve the power added efficiency of an RF power module having an amplifier element composed of a silicon power MOSFET, the on resistance and feedback capacitance, which were conventionally in a trade-off relationship, are reduced simultaneou... | 02/13/2007 |
| 7176526 | Semiconductor device, method for producing the same, and information processing apparatus A semiconductor device 1910 comprises a semiconductor substrate 100 including an isolation region 101 and an active region 102, a gate electrode 104 provided on the active region 102 via a gate insulating film 103, pa... | 02/13/2007 |
| 7173306 | Vertical semiconductor component having a drift zone having a field electrode, and method for fabricating such a drift zone The invention relates to a method for fabricating a drift zone of a vertical semiconductor component and to a vertical semiconductor component having the following features: a semiconductor body (100) having a first side ( | 02/06/2007 |
| 7157757 | Semiconductor constructions The invention includes semiconductor constructions, methods of forming gatelines, and methods of forming transistor structures. The invention can include, for example, a damascene method of forming a gateline. A thin segment of dielectric material is formed between ... | 01/02/2007 |
| 7154146 | Dielectric plug in mosfets to suppress short-channel effects The invention provides a technique to fabricate a dielectric plug in a MOSFET. The invention includes apparatus and systems that include one or more devices including a MOSFET having a dielectric plug. The dielectric plug is fabricated by forming an oxide layer over... | 12/26/2006 |
| 7135743 | Electrostatic discharge protection device with complementary dual drain implant Off-chip driver (OCD) NMOS transistors with ESD protection are formed by interposing an P-ESD implant between the N+ drain regions of OCD NMOS transistors and the N-well such that the P-ESD surrounds a section of the N-well. The P-ESD implant is dosed less than the ... | 11/14/2006 |
| 7126156 | Thin film transistor display device with integral control circuitry A semiconductor device includes a control circuit for carrying out gamma correction of a supplied signal, and a memory for storing data used in the gamma correction. The control circuit and the memory are constituted by TFTs, and are integrally formed on the same in... | 10/24/2006 |
| 7109546 | Horizontal memory gain cells A gain cell for a memory circuit, a memory circuit formed from multiple gain cells, and methods of fabricating such gain cells and memory circuits. The memory gain cell includes a storage capacitor, a write device electrically coupled with the storage capacitor for ... | 09/19/2006 |
| 7105851 | Nanotubes for integrated circuits One or more semiconducting or conducting regions of a device such as a transistor may comprise molecular materials such as nanotubes or similar materials. Regions of a conductive alignment pattern used to align the nanotubes may be proximate to one or more ends of t... | 09/12/2006 |
| 7101762 | Self-aligned double gate mosfet with separate gates A structure and method of manufacturing a double-gate integrated circuit which includes forming a laminated structure having a channel layer and first insulating layers on each side of the channel layer, forming openings in the laminated structure, forming drain and... | 09/05/2006 |
| 7098717 | Gate triggered ESD clamp The clamp circuit of the present invention comprises a low voltage, thin oxide MOS transistor and a trigger element comprising a timing element and at least one inverter. The source and drain of the MOS transistor are connected between a first node and a second node... | 08/29/2006 |
| 7091097 | End-of-range defect minimization in semiconductor device A method of fabricating a semiconductor device comprises forming a gate electrode over a substrate and forming deep amorphous regions within the substrate. And implanting dopants to form deep source/drain regions at a depth less than that of the deep amorphous regio... | 08/15/2006 |
| 7087509 | Method of forming a gate electrode on a semiconductor device and a device incorporating same The present invention is directed to a semiconductor device having a gate electrode includes of a plurality of sidewalls, each having a recess formed therein. The present invention is also directed to a method of forming a semiconductor device. In one illustrative e... | 08/08/2006 |
