Famous Patents
The ice cream cone was invented at the St. Louis Worlds Fair by Ernest Hamwi in 1904. His waffle booth was next to an ice cream vendor who ran short of dishes. Hamwi rolled a waffle to hold ice cream and the cone was born.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 8125031 | Low on-resistance lateral double-diffused MOS device A lateral-double diffused MOS device is provided. The device includes: a first well having a first conductive type and a second well having a second conductive type disposed in a substrate and adjacent to each other; a drain and a source regions having the first con... | 02/28/2012 |
| 8053836 | Oxide semiconductor thin-film transistor An oxide semiconductor thin-film transistor, comprising: a source electrode and a drain electrode formed on a substrate; a composite semiconductor active layer formed between the source electrode and the drain electrode; a gate dielectric layer formed on the source ... | 11/08/2011 |
| 7915679 | Light-emitting devices including a nonperiodic pattern Light-emitting devices, and related components, systems and methods are disclosed. In some embodiments, the light-emitting devices include a multi-layer stack of materials. The stack of materials includes a light-generating region and a first layer supported by the ... | 03/29/2011 |
| 7816734 | Field-effect transistor including localized halo ion regions, and semiconductor memory, memory card, and system including the same A field-effect transistor including localized halo ion regions that can optimize HEIP characteristics and GIDL characteristics. The field-effect transistor includes a substrate, an active region, a gate structure, and halo ion regions. The active region includes sou... | 10/19/2010 |
| 7566934 | Semiconductor device to suppress leak current at an end of an isolation film A semiconductor device is formed on an SOI substrate having a silicon layer formed on an insulating layer. A transistor element is formed in the silicon layer of the SOI substrate. An isolation film for electrically isolating the transistor element is formed in the ... | 07/28/2009 |
| 7560775 | Transistor and transistor manufacturing method In a transistor of the invention, at a boundary between gate oxide 112 formed on a silicon substrate 101 of a device formation region 10 and a device isolation film 110 adjoining the gate oxide 112, a thickness D′ of the gate ele... | 07/14/2009 |
| 7508032 | High voltage device with low on-resistance A high-voltage transistor device has a first well region with a first conductivity type in a semiconductor substrate, and a second well region with a second conductivity type in the semiconductor substrate substantially adjacent to the first well region. A field rin... | 03/24/2009 |
| 7436035 | Method of fabricating a field effect transistor structure with abrupt source/drain junctions Microelectronic structures embodying the present invention include a field effect transistor (FET) having highly conductive source/drain extensions. Formation of such highly conductive source/drain extensions includes forming a passivated recess which is back filled... | 10/14/2008 |
| 7417285 | Semiconductor device having a trench capacitor and a MOSFET connected by a diffusion layer and manufacturing method thereof A semiconductor device comprises a semiconductor substrate having a first conductivity type, a trench capacitor, provided in the semiconductor substrate, having a charge storage region, a gate electrode provided on the semiconductor substrate via a gate insulating f... | 08/26/2008 |
| 7348599 | Semiconductor device and manufacturing method thereof A p channel TFT of a driving circuit has a single drain structure and its n channel TFT, a GOLD structure or an LDD structure. A pixel TFT has the LDD structure. A pixel electrode disposed in a pixel portion is connected to the pixel TFT through a hole bored in at l... | 03/25/2008 |
| 7339235 | Semiconductor device having SOI structure and manufacturing method thereof A fine semiconductor device having a short channel length while suppressing a short channel effect. Linearly patterned or dot-patterned impurity regions 104 are formed in a channel forming region 103 so as to be generally parallel with the channel dire... | 03/04/2008 |
| 7332770 | Semiconductor device A semiconductor device of this invention is a vertical power MOSFET having a plurality of first trenches where a trench gate is formed. It has a first column region of a second conductivity type placed beneath the first trenches and formed vertically in an epitaxial... | 02/19/2008 |
| 7329922 | Dual-gate metal-oxide semiconductor device An MOS device includes first and second source/drain regions of a first conductivity type formed in a semiconductor layer of a second conductivity type proximate an upper surface of the semiconductor layer, the first and second source/drain regions being spaced apar... | 02/12/2008 |
| 7326609 | Semiconductor device and fabrication method A method and apparatus for manufacturing a semiconductor device is provides a substrate having a first region and a second region. A sacrificial first gate is formed in the first region. Source/drain are formed in the first region. A second region gate dielectric is... | 02/05/2008 |
| 7323753 | MOS transistor circuit and voltage-boosting booster circuit To an output of an NMOS having one end connected to a power source, a capacitor and a PMOS are connected. A capacitor is connected to the output of the PMOS. The NMOS and the PMOS are turned on alternately. A pulse is applied to other end of the capacitor which is c... | 01/29/2008 |
| 7317223 | Memory device and method of manufacturing the same In one embodiment, a memory device includes a semiconductor substrate, a first region formed in a predetermined region of the semiconductor substrate, and in which a plurality of memory transistors are disposed, and a second region adjacent to the first region, and ... | 01/08/2008 |
| 7317230 | Fin FET structure A fin FET structure employs a negative word line scheme. A gate electrode of a fin FET employs an electrode doped with n+ impurity, and a channel doping for a control of threshold voltage is not executed, or the channel doping is executed by a low density, thereby r... | 01/08/2008 |
| 7312500 | Manufacturing method of semiconductor device suppressing short-channel effect An ideal step-profile in a channel region is realized easily and reliably, whereby suppression of the short-channel effect and prevention of mobility degradation are achieved together. A silicon substrate is amorphized to a predetermined depth from a semiconductor f... | 12/25/2007 |
| 7312125 | Fully depleted strained semiconductor on insulator transistor and method of making the same An integrated circuit includes multiple layers. A semiconductor-on-insulator (SOI) wafer can be used to house transistors. Two substrates or wafers can be bonded to form the multiple layers. A strained semiconductor layer can be between a silicon germanium layer and... | 12/25/2007 |
| 7312483 | Thin film transistor device and method of manufacturing the same A semiconductor film is formed on a substrate. Subsequently, a resist film is formed on the semiconductor film, and dry etching is performed to the semiconductor film using the resist film as a mask. Due to the dry etching, the edge portion of the semiconductor film... | 12/25/2007 |
| 7312485 | CMOS fabrication process utilizing special transistor orientation Complementary metal oxide semiconductor transistors are formed on a silicon substrate. The substrate has a {100} crystallographic orientation. The transistors are formed on the substrate so that current flows in the channels of the transistors are parallel to the | 12/25/2007 |
| 7304354 | Buried guard ring and radiation hardened isolation structures and fabrication methods Semiconductor devices can be fabricated using conventional designs and process but including specialized structures to reduce or eliminate detrimental effects caused by various forms of radiation. Such semiconductor devices can include the one or more parasitic isol... | 12/04/2007 |
| 7304350 | Threshold voltage control layer in a semiconductor device A semiconductor device has a well region having a first conductivity type and formed in an upper portion of a semiconductor substrate, a gate insulating film and a gate electrode formed successively on the well region of the semiconductor substrate, a threshold volt... | 12/04/2007 |
| 7294551 | Semiconductor device and method for manufacturing the same A semiconductor device has a gate electrode formed on a P type semiconductor substrate via gate oxide films. A first low concentration (LN type) drain region is made adjacent to one end of the gate electrode. A second low concentration (SLN type) drain region is for... | 11/13/2007 |
| 7288819 | Stable PD-SOI devices and methods One aspect of the present subject matter relates to a partially depleted silicon-on-insulator structure. The structure includes a well region formed above an oxide insulation layer. In various embodiments, the well region is a multilayer epitaxy that includes a sili... | 10/30/2007 |
| 7288817 | Reverse metal process for creating a metal silicide transistor gate structure The present invention teaches a method of forming a MOSFET transistor having a silicide gate which is not subject to problems produced by etching a metal containing layer when forming the gate stack structure. A gate stack is formed over a semiconductor substrate co... | 10/30/2007 |
| 7285830 | Lateral bipolar junction transistor in CMOS flow An improved lateral bipolar junction transistor and a method of forming such a lateral bipolar transistor without added mask in CMOS flow on a p-substrate are disclosed. The CMOS flow includes patterning and n-well implants; pattern and implant pocket implants for c... | 10/23/2007 |
| 7282719 | Image pickup apparatus and radiation image pickup apparatus A reset method of a conversion element is improved, and the simplification of wiring and the improvement of an open area ratio of the conversion element by means of an image pickup apparatus including a plurality of pixels arranged on an insulating substrate, each o... | 10/16/2007 |
| 7276757 | Semiconductor device with shallow trench isolation and method of fabricating the same A semiconductor device includes a semiconductor substrate including a first upper surface, a first insulating film including an upper portion including a first side wall having a first upper end and a second upper surface having a second upper end, a second insulati... | 10/02/2007 |
| 7276773 | Power semiconductor device A power semiconductor device includes second semiconductor layers of a first conductivity type and third semiconductor layers of a second conductivity type alternately disposed on a first semiconductor layer of the first conductivity type. The device further include... | 10/02/2007 |
| 7268022 | Stable PD-SOI devices and methods One aspect of the present subject matter relates to a partially depleted silicon-on-insulator structure. The structure includes a well region formed above an oxide insulation layer. In various embodiments, the well region is a multilayer epitaxy that includes a sili... | 09/11/2007 |
| 7265416 | High breakdown voltage low on-resistance lateral DMOS transistor In accordance with the present invention, a metal oxide semiconductor (MOS) transistor has a substrate of a first conductivity type. A drift region of a second conductivity type extends over the substrate. A body region of the first conductivity type is in the drift... | 09/04/2007 |
| 7262450 | MFS type field effect transistor, its manufacturing method, ferroelectric memory and semiconductor device A MFS type field effect transistor includes a semiconductor layer, a PZT system ferroelectric layer formed on the semiconductor layer, a gate electrode formed on the PZT system ferroelectric layer, and an impurity layer composing a source or a drain, formed in the s... | 08/28/2007 |
| 7256462 | Semiconductor device The present invention is to provide a high-quality semiconductor device allowing independent control of threshold voltage values of gate electrodes of transistors which reside in a plurality of one-conductivity-type regions and in a reverse-conductivity-type region.... | 08/14/2007 |
| 7253478 | Semiconductor device The semiconductor device comprises: a semiconductor substrate (N+ substrate 110) containing a first conductivity type impurity implanted therein; a second conductivity type impurity-implanted layer (P+ implanted layer 114) at rela... | 08/07/2007 |
| 7253033 | Method of manufacturing a semiconductor device that includes implanting in multiple directions a high concentration region In a complete depletion type SOI transistor, the roll-off of a threshold value is suppressed, independently from the formation of an SOI film to be thinner. As for a semiconductor device (1), the impurity concentration in a channel formation portion (10 | 08/07/2007 |
| 7253062 | Semiconductor device with asymmetric pocket implants A semiconductor device (1) has a source (2) a gate (3) and a drain (4), a single deep-pocket ion implant (8) in a source-drain depletion region, and a single shallow-pocket ion implant (9) in the source-drain depletion regio... | 08/07/2007 |
| 7245152 | Voltage-level shifter In a voltage-level shifter, an input line is configured to convey an input voltage to be shifted. A pair of transistors is coupled to and is configured to receive the input voltage from the input line. There is a first side and a second side, with each side comprisi... | 07/17/2007 |
| 7235810 | Semiconductor device and method of fabricating the same There is provided a crystalline TFT in which reliability comparable to or superior to a MOS transistor can be obtained and excellent characteristics can be obtained in both an on state and an off state. A gate electrode of the crystalline TFT is formed of a laminate... | 06/26/2007 |
| 7232721 | Structures and methods for enhancing capacitors in integrated circuits Systems, devices, structures, and methods are described that inhibit dielectric degradation at high temperatures. An enhanced capacitor is discussed. The enhanced capacitor includes a first electrode, a dielectric that includes ditantalum pentaoxide, and a second el... | 06/19/2007 |
