Class 257/344 - With lightly doped portion of drain region adjacent channel (e.g., LDD structure)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: Subject matter wherein the short channel IGFET has a lightly
No. of patents: 1160
Last issue date: 02/16/2010

«First «Previous1 2 3 4 5 6 7 8 9 10 11 Next»Last»

Number	Title	Issue Date
7663187	Semiconductor device and method of fabricating the same An extension region is formed by ion implantation under masking by a gate electrode, and then a substance having a diffusion suppressive function over an impurity contained in a source-and-drain is implanted under masking by the gate electrode and a first sidewall s...	02/16/2010
7659580	Semiconductor device and manufacturing method thereof It is an object of the present invention to obtain a transistor with a high ON current including a silicide layer without increasing the number of steps. A semiconductor device comprising the transistor includes a first region in which a thickness is increased from ...	02/09/2010
7655983	SOI FET with source-side body doping An SOI FET device with improved floating body is proposed. Control of the body potential is accomplished by having a body doping concentration next to the source electrode higher than the body doping concentration next to the drain electrode. The high source-side do...	02/02/2010
7649226	Source and drain structures and manufacturing methods A semiconductor structure includes a semiconductor substrate; a first gate dielectric on the semiconductor substrate; a first gate electrode over the first gate dielectric; a first lightly doped source or drain (LDD) region in the semiconductor substrate and adjacen...	01/19/2010
7633124	Semiconductor device and method of manufacturing thereof A silicon nitride film having a thickness of 3 nm or less is formed on the surfaces of a P-well and N-well, as well as on the upper and side surfaces of a gate electrode, in which the silicon nitride film can be formed, for example, by exposing the surface of the P-...	12/15/2009
7629648	Semiconductor memory device and manufacturing method thereof The disclosure concerns a semiconductor memory device including an insulating film; a semiconductor layer provided on the insulating film; a source layer and a drain layer formed on the semiconductor layer; a body region provided between the source layer and the dra...	12/08/2009
7602019	Drive circuit and drain extended transistor for use therein A transistor comprises a source region of a first conductivity type and electrically communicating with a first semiconductor region. The transistor also comprises a drain region of the first conductivity type and electrically communicating with a second semiconduct...	10/13/2009
7592669	Semiconductor device with MISFET that includes embedded insulating film arranged between source/drain regions and channel With the objective of suppressing or preventing a kink effect in the operation of a semiconductor device having a high breakdown voltage field effect transistor, n+ type semiconductor regions, each having a conduction type opposite to p+ type s...	09/22/2009
7586153	Technique for forming recessed strained drain/source regions in NMOS and PMOS transistors By forming a strained semiconductor layer in a PMOS transistor, a corresponding compressively strained channel region may be achieved, while, on the other hand, a corresponding strain in the NMOS transistor may be relaxed. Due to the reduced junction resistance caus...	09/08/2009
7554156	Semiconductor device having a field effect transistor using a high dielectric constant gate insulating film and manufacturing method of the same In a method for manufacturing a semiconductor device having an N-channel field effect transistor, the N-channel field effect transistor is formed by a process including the steps of forming a high dielectric constant gate insulating film on a substrate, forming a ga...	06/30/2009
7544997	Multi-layer source/drain stressor A method for forming a semiconductor device includes forming a recess in a source region and a recess in a drain region of the semiconductor device. The method further includes forming a first semiconductor material layer in the recess in the source region and a sec...	06/09/2009
7528445	Wing gate transistor for integrated circuits A system is provided for forming a semiconductor device. Layers of gate dielectric material, gate material, and cap material are formed on a semiconductor substrate. The cap material and a portion of the gate material are processed to form a cap and a gate body port...	05/05/2009
7514744	Semiconductor device including carrier accumulation layers A semiconductor device includes a gate structure on a channel region of a semiconductor substrate adjacent to a source/drain region therein and a surface insulation layer directly on the source/drain region of the substrate adjacent to the gate structure. The device...	04/07/2009
7511340	Semiconductor devices having gate structures and contact pads that are lower than the gate structures Semiconductor devices have gate structures on a semiconductor substrate with first spacers on sidewalls of the respective gate structures. First contact pads are positioned between the gate structures and have heights lower than the heights of the gate structures. S...	03/31/2009
7492006	Semiconductor transistors having surface insulation layers and methods of fabricating such transistors Semiconductor devices having a transistor and methods of fabricating such devices are disclosed. The device may include a gate pattern formed on a substrate, spacers formed on sidewalls of the gate pattern, a surface insulation layer that may contact the substrate i...	02/17/2009
7446377	Transistors and manufacturing methods thereof Transistors and manufacturing methods thereof are disclosed. An example transistor includes a semiconductor substrate divided into device isolation regions and a device active region. The example transistor includes a gate insulating film formed in the active region...	11/04/2008
7442991	Display including casing and display unit This invention provides a semiconductor device having high operation performance and high reliability. An LDD region 707 overlapping with a gate wiring is arranged in an n-channel TFT 802 forming a driving circuit, and a TFT structure highly resistant ...	10/28/2008
7439124	Method of manufacturing a semiconductor device and semiconductor device Method of manufacturing a semiconductor device includes: forming a substrate protection film to cover an n-type FET forming region having a first gate electrode and a p-type FET forming region having a second gate electrode; opening the p-type FET forming region by ...	10/21/2008
7436026	Semiconductor device comprising a superlattice channel vertically stepped above source and drain regions A semiconductor device may include a semiconductor substrate and at least one metal oxide semiconductor field-effect transistor (MOSFET). The at least one MOSFET may include spaced apart source and drain regions in the semiconductor substrate, and a superlattice cha...	10/14/2008
7429771	Semiconductor device having halo implanting regions A MIS-type semiconductor device includes a p-type semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, and n-type diffused source and drain layers formed in regions of the semicon...	09/30/2008
7429769	Recessed channel field effect transistor (FET) device A method for forming a field effect transistor device employs a self-aligned etching of a semiconductor substrate to form a recessed channel region in conjunction with a pair of raised source/drain regions. The method also provides for forming and thermally annealin...	09/30/2008
RE40486	Self-aligned non-volatile memory cell Disclosed is a self-aligned non-volatile memory cell including a small sidewall spacer electrically coupled and being located next to a main floating gate region. Both the small sidewall spacer and the main floating gate region are formed on a substrate and both for...	09/09/2008
7405450	Semiconductor devices having high conductivity gate electrodes with conductive line patterns thereon Semiconductor devices that include a semiconductor substrate and a gate line are provided. The gate line is on the semiconductor substrate and includes a gate insulation pattern and a gate electrode which are stacked on the substrate in the order named. A spacer is ...	07/29/2008
7405458	Asymmetric field transistors (FETs) A semiconductor structure and a method for forming the same. The structure includes (a) a semiconductor channel region, (b) a semiconductor source block in direct physical contact with the semiconductor channel region; (c) a source contact region in direct physical ...	07/29/2008
7400018	End of range (EOR) secondary defect engineering using chemical vapor deposition (CVD) substitutional carbon doping A method for incorporating carbon into a wafer at the interstitial a-c silicon interface of the halo doping profile is achieved. A bulk silicon substrate is provided. A carbon-doped silicon layer is deposited on the bulk silicon substrate. An epitaxial silicon layer...	07/15/2008
7396717	Method of forming a MOS transistor A method of forming a MOS transistor, in which a co-implantation is performed to implant an implant into a source region and a drain region or a halo implanted region to effectively prevent dopants from over diffusion in the source region and the drain region or the...	07/08/2008
7388228	Display device and method of manufacturing the same Thin film transistors for a display device each include a semiconductor layer made of polysilicon having a channel region, drain and source regions at both sides of the channel region and doped with impurity of high concentration, and an LDD region arranged either b...	06/17/2008
7382021	Insulated gate field-effect transistor having III-VI source/drain layer(s) A transistor includes one or more channel taps containing a stack consisting at least in part of a semiconductor an interfacial III-VI layered compound and a conductor. The III-VI compound consists primarily of atoms from Groups IIIA-B and from Group VIA of the Peri...	06/03/2008
7368792	MOS transistor with elevated source/drain structure In a metal-oxide semiconductor (MOS) transistor with an elevated source/drain structure and in a method of fabricating the MOS transistor with the elevated source/drain structure using a selective epitaxy growth (SEG) process, a source/drain extension junction is fo...	05/06/2008
7364995	Method of forming reduced short channel field effect transistor A method for manufacturing a semiconductor device capable of reducing a short channel effect, whereby the semiconductor device includes a pair of impurity regions for a source and a drain formed on a semiconductor substrate, a gate having a gate electrode used to co...	04/29/2008
7365390	Method of fabricating recess transistor in integrated circuit device and recess transistor in integrated circuit device fabricated by the same Provided is a method of fabricating a recess transistor in an integrated circuit device. In the provided method, a device isolation region, which contacts to the sidewall of a gate trench and a substrate region remaining between the sidewall of the device isolation ...	04/29/2008
7365393	Semiconductor device and fabrication method thereof This invention provides a semiconductor device having high operation performance and high reliability. An LDD region 707 overlapping with a gate wiring is arranged in an n-channel TFT 802 forming a driving circuit, and a TFT structure highly resistant ...	04/29/2008
7365402	LDMOS transistor An LDMOS semiconductor transistor structure comprises a substrate having an epitaxial layer of a first conductivity type, a source region extending from a surface of the epitaxial layer of a second conductivity type, a lightly doped drain region within the epitaxial...	04/29/2008
7361564	Method of manufacturing high-voltage device A method of manufacturing a high-voltage device DDD (Double Doped Drain) ion implantation process is performed at a tilt angle in order to form a smooth junction profile. Accordingly, the intensity of an electric field can be reduced and breakdown voltage margin can...	04/22/2008
7361578	Method to form large grain size polysilicon films by nuclei-induced solid phase crystallization A method to enhance grain size in polysilicon films while avoiding formation of hemispherical grains (HSG) is disclosed. The method begins by depositing a first amorphous silicon film, then depositing silicon nuclei, which will act as nucleation sites, on the amorph...	04/22/2008
7355245	Structure for reducing overlap capacitance in field effect transistors A field effect transistor (FET) device includes a gate conductor formed over a semiconductor substrate, a source region having a source extension that overlaps and extends under the gate conductor, and a drain region having a drain extension that overlaps and extend...	04/08/2008
7354848	Poly-silicon-germanium gate stack and method for forming the same A CMOS gate stack that increases the inversion capacitance compared to a conventional CMOS gate stack has been described. Using a poly-SiGe gate, instead of the conventional poly-Si gate near the gate dielectric layer, increases the amount of implanted dopant that c...	04/08/2008
7354838	Technique for forming a contact insulation layer with enhanced stress transfer efficiency By removing an outer spacer, used for the formation of highly complex lateral dopant profiles, prior to the formation of metal silicide, a high degree of process compatibility with conventional processes is obtained, while at the same time a contact liner layer may ...	04/08/2008
7351627	Method of manufacturing semiconductor device using gate-through ion implantation Disclosed herein is a method of manufacturing a semiconductor device via gate-through ion implantation, comprising forming a gate stack on a semiconductor substrate and performing ion implantation for control of the threshold voltage and junction ion implantation fo...	04/01/2008
7348599	Semiconductor device and manufacturing method thereof A p channel TFT of a driving circuit has a single drain structure and its n channel TFT, a GOLD structure or an LDD structure. A pixel TFT has the LDD structure. A pixel electrode disposed in a pixel portion is connected to the pixel TFT through a hole bored in at l...	03/25/2008

«First «Previous1 2 3 4 5 6 7 8 9 10 11 Next»Last»

PatentStorm

Quotables

PatentStorm News

Class 257/344 - With lightly doped portion of drain region adjacent channel (e.g., LDD structure)