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| Number | Title | Issue Date |
| 8129779 | Trench gate type VDMOSFET device with thicker gate insulation layer portion for reducing gate to source capacitance A semiconductor device according to the present invention includes a semiconductor layer. A first conductivity type region is formed on a base layer portion of the semiconductor layer. A body region of a second conductivity type is formed on the semiconductor layer ... | 03/06/2012 |
| 8115252 | Elimination of gate oxide weak spot in deep trench A MOSFET with a 0.7˜2.0 micrometers deep trench is formed by first carrying out a processing step of opening a trench in a semiconductor substrate. A thick insulator layer is then deposited in the trench such that the film at the bottom of the trench is much thicke... | 02/14/2012 |
| 8101995 | Integrated MOSFET and Schottky device A power semiconductor device that includes a trench power MOSFET with deep source field electrodes and an integrated Schottky diode. ... | 01/24/2012 |
| 7834395 | 3-D channel field-effect transistor, memory cell and integrated circuit A field-effect transistor includes a source region, a drain region and a channel region between the source and the drain region. A gate electrode is also arranged between them, where a lower edge of the gate electrode is formed below a lower edge of at least one of ... | 11/16/2010 |
| 7612408 | MOS transistor device The invention relates to a MOS transistor device of the trench type, in which, in a semiconductor region of a first conductivity type, within a deep gate trench extending in the vertical direction of the semiconductor region, a vertical gate electrode and a gate oxi... | 11/03/2009 |
| 7598569 | Semiconductor device A semiconductor device including: a semiconductor layer; a transistor formed in the semiconductor layer and including a gate insulating layer and a gate electrode, the transistor being a high voltage transistor in which an insulating layer having a thickness greater... | 10/06/2009 |
| 7579650 | Termination design for deep source electrode MOSFET A power semiconductor device that includes a plurality of source trenches that extend to a depth below the gate electrodes and a termination region that includes a termination trench that is as deep as the source trenches. ... | 08/25/2009 |
| 7557409 | Super trench MOSFET including buried source electrode In a trench MOSFET, the lower portion of the trench contains a buried source electrode, which is insulated from the epitaxial layer and semiconductor substrate but in electrical contact with the source region. When the MOSFET is in an “off” condition, the bias o... | 07/07/2009 |
| 7439183 | Method of manufacturing a semiconductor device, and a semiconductor substrate A method of manufacturing a semiconductor device. In the method, a thin film is formed on an Si substrate having face orientation (100), that part of the thin film, which lies on an element-isolating region, is removed. Then, the Si substrate is subjected to ... | 10/21/2008 |
| 7436017 | Semiconductor integrated circuit using a selective disposable spacer Methods of manufacturing a semiconductor integrated circuit using selective disposable spacer technology and semiconductor integrated circuits manufactured thereby: The method includes forming a plurality of gate patterns on a semiconductor substrate. Gap regions be... | 10/14/2008 |
| 7435647 | NOR-type flash memory device and manufacturing method thereof A flash memory device that has a structure capable of preventing gate stack damage, and a method of manufacturing the same, is presented. The method includes forming a first photo resist pattern to open a common source region on a substrate where a shallow trench is... | 10/14/2008 |
| 7432189 | Device with self aligned gaps for capacitance reduction A method for reducing capacitances between semiconductor device wirings is provided. A sacrificial layer is formed over a dielectric layer. A plurality of features are etched into the sacrificial layer and dielectric layer. The features are filled with a filler mate... | 10/07/2008 |
| 7427794 | Tri-gate devices and methods of fabrication The present invention is a semiconductor device comprising a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite ... | 09/23/2008 |
| 7408223 | Trench insulated gate field effect transistor The invention relates to a trench MOSFET with drain (8), sub-channel region (10) body (12) and source (14). The sub-channel region is doped to be the same conductivity type as the body (12), but of lower doping density. A field pla... | 08/05/2008 |
| 7408234 | Semiconductor device and method for manufacturing the same An object of the present invention is to provide a semiconductor device that is able to realize a low on-resistance maintaining a high drain-to-source breakdown voltage, and a method for manufacturing thereof, the present invention including: a supporting substrate;... | 08/05/2008 |
| 7397082 | Semiconductor device having shallow trenches and method for manufacturing the same The capacitance between the gate electrode film and the drain layer of semiconductor device is reduced while keeping the resistance low, with the breakdown voltage of the gate insulating film also being maintained at a sufficient level. A trench 10 is formed ... | 07/08/2008 |
| 7390717 | Trench power MOSFET fabrication using inside/outside spacers A fabrication process for a trench type power semiconductor device includes forming inside spacers over a semiconductor surface. Using the spacers as masks, trenches with gates are formed in the semiconductor body. After removing the spacers, source implants are for... | 06/24/2008 |
| 7382018 | 3-Dimensional flash memory device and method of fabricating the same In an embodiment, a 3-dimensional flash memory device includes: a gate extending in a vertical direction on a semiconductor substrate; a charge storing layer surrounding the gate; a silicon layer surrounding the charge storing layer; a channel region vertically form... | 06/03/2008 |
| 7378707 | Scalable high density non-volatile memory cells in a contactless memory array A plurality of mesas are formed in the substrate. Each pair of mesas forms a trench. A plurality of diffusion areas are formed in the substrate. A mesa diffusion area is formed in each mesa top and a trench diffusion area is formed under each trench. A vertical, non... | 05/27/2008 |
| 7371645 | Method of manufacturing a field effect transistor device with recessed channel and corner gate device Fabrication of recessed channel array transistors (RCAT) with a corner gate device includes forming pockets between a semiconductor fin that includes a gate groove and neighboring shallow trench isolations that extend along longs sides of the semiconductor fin. A pr... | 05/13/2008 |
| 7368353 | Trench power MOSFET with reduced gate resistance A method for manufacturing a trench type power semiconductor device which includes process steps for forming proud gate electrodes in order to decrease the resistivity thereof. ... | 05/06/2008 |
| 7368783 | Semiconductor device A semiconductor device includes a semiconductor substrate of a first conductivity type, a lightly-doped semiconductor layer of the first conductivity type formed on the first major surface of the substrate, a first semiconductor region of the first conductivity type... | 05/06/2008 |
| 7365392 | Semiconductor device with integrated trench lateral power MOSFETs and planar devices Gate electrodes of a TLPM and gate electrodes of planar devices are formed by patterning a same polysilicon layer. Drain electrode(s) and source electrode(s) of the TLPM and drain electrodes and source electrodes of the planar devices are formed by patterning a same... | 04/29/2008 |
| 7364994 | Method for manufacturing a superjunction device with wide mesas A method of manufacturing a semiconductor device includes providing semiconductor substrate having trenches and mesas. At least one mesa has first and second sidewalls. The method includes angularly implanting a dopant of a second conductivity into the first sidewal... | 04/29/2008 |
| 7352036 | Semiconductor power device having a top-side drain using a sinker trench A semiconductor power device includes a substrate of a first conductivity type and an epitaxial layer of the first conductivity type over and in contact with the substrate. A first trench extends into and terminates within the epitaxial layer. A sinker trench extend... | 04/01/2008 |
| 7348628 | Vertical channel semiconductor devices and methods of manufacturing the same Vertical channel semiconductor devices include a semiconductor substrate with a pillar having an upper surface. An insulated gate electrode is around a periphery of the pillar. The insulated gate electrode has an upper surface at a vertical level lower than the uppe... | 03/25/2008 |
| 7339235 | Semiconductor device having SOI structure and manufacturing method thereof A fine semiconductor device having a short channel length while suppressing a short channel effect. Linearly patterned or dot-patterned impurity regions 104 are formed in a channel forming region 103 so as to be generally parallel with the channel dire... | 03/04/2008 |
| 7335565 | Metal-oxide-semiconductor device having improved performance and reliability A method for forming a MOS device includes the steps of forming a gate proximate an upper surface of a semiconductor layer, the semiconductor layer including a substrate of a first conductivity type and a second layer of a second conductivity type; forming first and... | 02/26/2008 |
| 7332755 | Transistor structure of memory device and method for fabricating the same A memory device includes an active area protruding from a semiconductor substrate. A recess is formed in the active area. A field oxide layer is formed on the semiconductor substrate. A gate electrode extends across the active area while being overlapped with the re... | 02/19/2008 |
| 7326961 | Semiconductor device and manufacturing method therefor To provide devices relating to a manufacturing method for a semiconductor device using a laser crystallization method, which is capable of reducing a cost involved in a design change, preventing a grain boundary from developing in a channel formation region of a TFT... | 02/05/2008 |
| 7326995 | Trench MIS device having implanted drain-drift region and thick bottom oxide A trench MIS device is formed in a P-epitaxial layer that overlies an N+ substrate. In one embodiment, the device includes a thick oxide layer at the bottom of the trench and an N-type drain-drift region that extends from the bottom of the trench to the substrate. T... | 02/05/2008 |
| 7323745 | Top drain MOSFET A power MOSFET is disclosed in which the source and drain regions are reversed from their usual positions and the drain is on the top of the chip (the surface containing the junction pattern diffusions) and the source is on the bottom of the chip. A plurality of spa... | 01/29/2008 |
| 7323386 | Method of fabricating semiconductor device containing dielectrically isolated PN junction for enhanced breakdown characteristics A semiconductor device includes a field shield region that is doped opposite to the conductivity of the substrate and is bounded laterally by dielectric sidewall spacers and from below by a PN junction. For example, in a trench-gated MOSFET the field shield region m... | 01/29/2008 |
| 7301200 | Trench FET with self aligned source and contact A trench type power MOSgated device has a plurality of spaced trenches lined with oxide and filled with conductive polysilicon. The tops of the polysilicon fillers are below the top silicon surface and are capped with a deposited oxide the top of which is flush with... | 11/27/2007 |
| 7301636 | Miniaturized system and method for measuring optical characteristics A miniaturized spectrometer/spectrophotometer system and methods are disclosed. A probe tip including one or more light sources and a plurality of light receivers is provided. A first spectrometer system receives light from a first set of the plurality of light rece... | 11/27/2007 |
| 7291884 | Trench MIS device having implanted drain-drift region and thick bottom oxide A trench MIS device is formed in a P-epitaxial layer that overlies an N-epitaxial layer and an N+ substrate. In one embodiment, the device includes a thick oxide layer at the bottom of the trench and an N-type drain-drift region that extends from the bottom of the t... | 11/06/2007 |
| 7282412 | Trench semiconductor device having gate oxide layer with multiple thicknesses and processes of fabricating the same The a trench semiconductor device such as a power MOSFET the high electric field at the corner of the trench is diminished by increasing the thickness of the gate oxide layer at the bottom of the trench. Several processes for manufacturing such devices are described... | 10/16/2007 |
| 7279757 | Double-sided extended drain field effect transistor A double-sided extended drain field effect transistor that includes a gate terminal overlying a channel region in a substrate. The substrate includes a drain region of a first carrier type that is laterally separated from the channel region by a first RESURF region ... | 10/09/2007 |
| 7279725 | Vertical diode structures A method of making a vertical diode structure is provided, the vertical diode structure having associated therewith a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer covers the interio... | 10/09/2007 |
| 7279710 | Structure and method of fabricating a transistor having a trench gate An integrated circuit transistor is fabricated with a trench gate having nonconductive sidewalls. The transistor is surrounded by an isolation trench filled with a nonconductive material. The sidewalls of the gate trench are formed of the nonconductive material and ... | 10/09/2007 |
