Microwave Oven With Removable Storage Cassette in Dashboard of Motor Vehicle
A microwave oven adapted for use within a motor vehicle dashboard area. The microwave oven has a removable storage cassette, and slidable platforms for securing and serving containers of beverages and foods.
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| Number | Title | Issue Date |
| 8154075 | Nonvolatile semiconductor memory device and method for manufacturing the same A split gate type nonvolatile semiconductor memory device having a FinFET structure includes a semiconductor substrate, parallel trenches on a surface of the semiconductor substrate, and select and memory gate electrodes perpendicular to the trenches. While either t... | 04/10/2012 |
| 8148776 | Transistor with a passive gate Disclosed is a device having a transistor that includes a source, a drain, a channel region extending between the source and the drain, a gate disposed near the channel region, and a conductive member disposed opposite of the channel region from the gate. The conduc... | 04/03/2012 |
| 8138544 | Castellated gate MOSFET tetrode capable of fully-depleted operation A castellated-gate MOSFET tetrode device capable of fully depleted operation is disclosed. The device includes a semiconductor substrate region having an upper portion with a top surface and a lower portion with a bottom surface. A source region and a drain region a... | 03/20/2012 |
| 8138543 | Hybrid FinFET/planar SOI FETs A circuit structure is disclosed which contains least one each of three different kinds of devices in a silicon layer on insulator (SOI): a planar NFET device, a planar PFET device, and a FinFET device. A trench isolation surrounds the planar NFET device and the pla... | 03/20/2012 |
| 8129778 | Semiconductor devices and methods for making the same Semiconductor devices and methods for making such devices that are especially suited for high-frequency applications are described. The semiconductor devices combine a SIT (or a junction field-effect transistor [JFET]) architecture with a PN super-junction structure... | 03/06/2012 |
| 8120103 | Semiconductor device with vertical gate and method for fabricating the same A semiconductor device includes a substrate; a plurality of active pillars formed over the substrate; bulb-type trenches, each of the bulb-type trenches formed inside the substrate between the active pillars; buried bit lines, each of the buried bit lines being form... | 02/21/2012 |
| 8106448 | NAND flash memory device A method of manufacturing a NAND flash memory device. A semiconductor substrate of a portion in which a source select line SSL and a drain select line DSL will be formed is recessed selectively or entirely to a predetermined depth. Accordingly, the channel length of... | 01/31/2012 |
| 8106447 | Semiconductor device and method of manufacturing the same Disclosed herein is a semiconductor device, including: a first semiconductor region of a first conductivity type; a second semiconductor region having pairs of first pillar regions of the first conductivity type, and second pillar regions of a second conductivity ty... | 01/31/2012 |
| 8076724 | Transistor structure having an active region and a dielectric platform region A semiconductor device is formed having lower gate-to-drain capacitance. The semiconductor device having an active region (1300) and a dielectric platform region (1310). A trench (80) is formed adjacent to a drain (20) of the semiconducto... | 12/13/2011 |
| 8067800 | Super-junction trench MOSFET with resurf step oxide and the method to make the same A super-junction trench MOSFET with Resurf Stepped Oxide is disclosed. The inventive structure can apply additional freedom for better optimization and manufacturing capability by tuning thick oxide thickness to minimize influence of charge imbalance, trapped charge... | 11/29/2011 |
| 8058686 | Semiconductor device including a columnar intermediate region and manufacturing method thereof A semiconductor device includes field effect transistors, each having a semiconductor layer formed on a major surface of a semiconductor substrate, a base region formed in a surface layer portion of a semiconductor layer, a source region formed in a surface layer po... | 11/15/2011 |
| 8049274 | Semiconductor integrated circuit and method of manufacturing the same A semiconductor integrated circuit includes a semiconductor substrate, a plurality of trenches formed to extend in one direction in the semiconductor substrate, at least one connecting trench connecting at least two of the plurality of trenches to each other, a plur... | 11/01/2011 |
| 8044460 | Electronic device with connecting structure A connecting structure for an electronic device includes an edge region of the device, a first trench and a second trench running toward the edge region, a first electrode within the first trench, and a second electrode within the second trench, the first and second... | 10/25/2011 |
| 8039896 | Semiconductor memory device with vertical channel formed on semiconductor pillars In a semiconductor memory device having a vertical channel transistor a body of which is connected to a substrate and a method of fabricating the same, the semiconductor memory device includes a semiconductor substrate including a plurality of pillars arranged space... | 10/18/2011 |
| 8035161 | Semiconductor component A semiconductor component resistant to the formation of a parasitic bipolar transistor and a method for manufacturing the semiconductor component using a reduced number of masking steps. A semiconductor material of N-type conductivity having a region of P-type condu... | 10/11/2011 |
| 8030703 | Field-effect transistor and method for manufacturing a field-effect transistor A field-effect transistor and a method for manufacturing a field-effect transistor is disclosed. One embodiment includes a substrate having a surface along which a trench is implemented, wherein the trench has a trench bottom and a trench edge. A source area is impl... | 10/04/2011 |
| 8022475 | Semiconductor device optimized to increase withstand voltage and reduce on resistance An ON resistance of a trench gate type transistor and a withstand voltage of a planar type transistor are optimized at the same time. Each of first and second regions of a semiconductor layer is formed by epitaxial growth on each of first and second regions of a sem... | 09/20/2011 |
| 8022474 | Semiconductor device A semiconductor device includes a source metallization, a source region of a first conductivity type in contact with the source metallization, a body region of a second conductivity type which is adjacent to the source region. The semiconductor device further includ... | 09/20/2011 |
| 8013389 | Three-dimensional nonvolatile memory devices having sub-divided active bars and methods of manufacturing such devices Nonvolatile memory devices are provided and methods of manufacturing such devices. In the method, conductive layers and insulating layers are alternatingly stacked on a substrate. A first sub-active bar is formed which penetrates a first subset of the conductive lay... | 09/06/2011 |
| 8008715 | Semiconductor device There is provided a semiconductor device comprising: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type provided on the first semiconductor layer of the first conductivity type; a semiconductor region... | 08/30/2011 |
| 7999312 | Insulated gate-type semiconductor device having a low concentration diffusion region A semiconductor 100 has a P− body region and an N− drift region in the order from an upper surface side thereof. A gate trench and a terminal trench passing through the P− body region are formed. The respective trenches are sur... | 08/16/2011 |
| 7964914 | Semiconductor device and method for fabricating the same including a gate insulation layer and conductive layer surrounding a pillar pattern A semiconductor device includes pillar patterns, a gate insulation layer surrounding the pillar patterns, and a conductive layer surrounding the gate insulation layer and connects neighboring gate insulation layers. ... | 06/21/2011 |
| 7952140 | Methods of fabricating semiconductor devices having multiple channel transistors and semiconductor devices fabricated thereby In methods of fabricating a semiconductor device having multiple channel transistors and semiconductor devices fabricated thereby, the semiconductor device includes an isolation region disposed within a semiconductor substrate and defining a first region. A pluralit... | 05/31/2011 |
| 7939886 | Trench gate power semiconductor device A trench gate power MOSFET (1) includes: an n−-type epitaxial layer (12); a p-type body region (20) formed in the vicinity of an upper surface of the n−-type epitaxial layer (12); a plurality of trenches (14 | 05/10/2011 |
| 7923775 | Semiconductor device and method for fabricating the same A semiconductor device includes a plurality of trench patterns formed over a substrate; gate insulation layers formed over sidewalls of the trench patterns; gate electrodes formed over the trench patterns; line patterns coupling the gate electrodes; and source and d... | 04/12/2011 |
| 7902598 | Two-sided surround access transistor for a 4.5F2 DRAM cell An isolation transistor having a grounded gate is formed between a first access transistor construction and a second access transistor construction to provide isolation between the access transistor constructions of a memory device. In an embodiment, the access tran... | 03/08/2011 |
| 7893489 | Semiconductor device having vertical MOSFET An ON-resistance of a semiconductor device including a vertical MOSFET whose source electrode, gate electrode, and drain electrode are formed on a single surface is reduced. A drift region which is lower in impurity concentration than a drain region is formed over t... | 02/22/2011 |
| 7872307 | Power MOSFET array A power metal-oxide-semiconductor field-effect transistor (MOSFET) array structure is provided. The power MOSFET array is disposed under a gate pad, and space under the gate pad can be well used to increase device integration. When the array and the conventional pow... | 01/18/2011 |
| 7872306 | Structure of trench MOSFET and method for manufacturing the same A trench MOSFET with copper metal connections includes a substrate provided with a plurality of trenches. A gate oxide layer is formed on the sidewalls and bottoms of the trenches. A conductive layer is filled in the trenches to be used as a gate of the MOSFET. A pl... | 01/18/2011 |
| 7863678 | Insulated-gate field-effect transistor An IGFET that can be turned off when a reverse voltage is applied. Included is a semiconductor substrate having formed therein an n-type drain region, p-type first body region, p−-type second body region, n-type first source region, and n+-ty... | 01/04/2011 |
| 7863677 | Semiconductor device and method of fabricating the same A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a plurality of active regions which are defined in a semiconductor substrate, a plurality of gate lines which are formed as zigzag lines, extend across the ac... | 01/04/2011 |
| 7863676 | Semiconductor devices and methods of fabricating the same A semiconductor device includes a device isolation layer in a semiconductor substrate, an active region defined by the device isolation layer, the active region including a main surface and a recess region including a bottom surface that is lower than the main surfa... | 01/04/2011 |
| 7859050 | Memory having a vertical access device Semiconductor memory devices having vertical access devices are disclosed. In some embodiments, a method of forming the device includes providing a recess in a semiconductor substrate that includes a pair of opposed side walls and a floor extending between the oppos... | 12/28/2010 |
| 7829944 | High-voltage vertical transistor with a multi-layered extended drain structure A high-voltage transistor with a low specific on-state resistance and that supports high voltage in the off-state includes one or more source regions disposed adjacent to a multi-layered extended drain structure which comprises extended drift regions separated from ... | 11/09/2010 |
| 7821061 | Silicon germanium and germanium multigate and nanowire structures for logic and multilevel memory applications A method to provide a transistor or memory cell structure. The method comprises: providing a substrate including a lower Si substrate and an insulating layer on the substrate; providing a first projection extending above the insulating layer, the first projection in... | 10/26/2010 |
| 7816730 | Semiconductor device and method for fabricating the same A semiconductor device comprises a fin-type active region defined by a semiconductor substrate having a device isolation structure, a recess formed over the fin-type active region, and a gate electrode including a silicon germanium (Si1-xGex) l... | 10/19/2010 |
| 7816731 | Segmented pillar layout for a high-voltage vertical transistor In one embodiment, a transistor fabricated on a semiconductor die includes a first section of transistor segments disposed in a first area of the semiconductor die, and a second section of transistor segments disposed in a second area of the semiconductor die adjace... | 10/19/2010 |
| 7808042 | Systems and devices including multi-gate transistors and methods of using, making, and operating the same Disclosed are methods, systems and devices, including a device having a digit line and a plurality of transistors each having one terminal connected to the digit line and another terminal disposed on alternating sides of the digit line. In some embodiments, each tra... | 10/05/2010 |
| 7800171 | Integrated circuit including a semiconductor device An integrated circuit including a semiconductor device is disclosed. One embodiment provides a load current component, having a multiplicity of trenches in a cell array. A sensor component is integrated into the cell array of the load current component and has a sen... | 09/21/2010 |
| 7800172 | Methods of forming semiconductor devices having multiple channel MOS transistors and related intermediate structures In a method of manufacturing a semiconductor device, a preliminary active pattern including gate layers and channel layers is formed on a substrate. The gate layers and the channel layers are alternatively stacked. A hard mask is formed on the preliminary active pat... | 09/21/2010 |