Bizarre Patents
A kissing shield comprised of a thin, flexible membrane and a frame or holder.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 8148771 | Semiconductor device and method to manufacture thereof A semiconductor device 100 includes a semiconductor substrate 14, a connection electrode 12 disposed on an upper surface of the semiconductor substrate 14 and connected to an integrated circuit thereon, a through electrode 20 which... | 04/03/2012 |
| 8148772 | Recessed channel array transistor (RCAT) structures Recessed channel array transistor (RCAT) structures and method of formation are generally described. In one example, an electronic device includes a semiconductor substrate, a first fin coupled with the semiconductor substrate, the first fin comprising a first sourc... | 04/03/2012 |
| 8148773 | Power semiconductor devices integrated with clamp diodes having separated gate metal pads to avoid breakdown voltage degradation A structure of power semiconductor device integrated with clamp diodes having separated gate metal pad is disclosed. The separated gate metal pads are wire bonded together on the gate lead frame. This improved structure can prevent the degradation of breakdown volta... | 04/03/2012 |
| 8129777 | Semiconductor device having a multi-channel type MOS transistor In a method of manufacturing a semiconductor device, an active channel pattern is formed on a substrate. The active channel pattern includes preliminary gate patterns and single crystalline silicon patterns that are alternately stacked with each other. A source/drai... | 03/06/2012 |
| 8063437 | Semiconductor device and method for producing the same A semiconductor device includes: a first semiconductor region formed on a substrate and having an upper surface and a side surface; a first impurity region of a first conductivity type formed in an upper portion of the first semiconductor region; a second impurity r... | 11/22/2011 |
| 8013384 | Method for manufacturing a high integration density power MOS device A process for the realization of a high integration density power MOS device includes the following steps of: providing a doped semiconductor substrate with a first type of conductivity; forming, on the substrate, a semiconductor layer with lower conductivity; formi... | 09/06/2011 |
| 8008711 | Insulated gate transistor incorporating diode A p-type base layer shaped like a well is formed for each of IGBT cells, and a p+-type collector layer and an n+-type cathode layer are formed on a surface opposite to a surface on which the p-type base layer is formed so as to be situated just... | 08/30/2011 |
| 8004035 | Dual stress liner device and method A dual stress liner manufacturing method and device is described. Overlapping stress liner layers of opposite effect (e.g., tensile versus compression) may be deposited over portions of the device, and the uppermost overlapping layer may be polished down in a proces... | 08/23/2011 |
| 7994567 | Semiconductor device and a method of manufacturing the same To reduce the size and improve the power added efficiency of an RF power module having an amplifier element composed of a silicon power MOSFET, the on resistance and feedback capacitance, which were conventionally in a trade-off relationship, are reduced simultaneou... | 08/09/2011 |
| 7982263 | Semiconductor device having a plurality of misfets formed on a main surface of a semiconductor substrate In a high frequency amplifying MOSFET having a drain offset region, the size is reduced and the on-resistance is decreased by providing conductor plugs 13 (P1) for leading out electrodes on a source region 10, a drain region 9 and leach-t... | 07/19/2011 |
| 7964910 | Planar field effect transistor structure having an angled crystallographic etch-defined source/drain recess and a method of forming the transistor structure Disclosed is a transistor that incorporates epitaxially deposited source/drain semiconductor films and a method for forming the transistor. A crystallographic etch is used to form recesses between a channel region and trench isolation regions in a silicon substrate.... | 06/21/2011 |
| 7943985 | Oxide semiconductor thin film transistors and fabrication methods thereof Oxide semiconductor thin film transistors (TFT) and methods of manufacturing the same are provided. The methods include forming a channel layer on a substrate, forming source and drain electrodes at opposing sides of the channel layer, and oxidizing a surface of the... | 05/17/2011 |
| 7939881 | Semiconductor device A semiconductor device includes a gate electrode formed through a gate insulating film provided on a first impurity region and a drift layer, and this gate electrode consists of two regions including a first conductivity type second impurity region opposed to the fi... | 05/10/2011 |
| 7936006 | Semiconductor device with backfilled isolation An MOS device has an embedded dielectric structure underlying an active portion of the device, such as a source extension or a drain extension. In an alternative embodiment, an embedded dielectric structure underlies the channel region of a MOS device, as well as th... | 05/03/2011 |
| 7932552 | Multiple source-single drain field effect semiconductor device and circuit Disclosed are embodiments of a variable-delay field effect transistor (FET) having multiple source regions that can be individually and selectively biased to provide an electrical connection to a single drain region. Delay is a function of which of the multiple sour... | 04/26/2011 |
| 7915670 | Asymmetric field effect transistor structure and method Disclosed are embodiments of an asymmetric field effect transistor structure and a method of forming the structure in which both series resistance in the source region (Rs) and gate to drain capacitance (Cgd) are reduced in order to provide opt... | 03/29/2011 |
| 7898023 | Recessed channel array transistor (RCAT) structures Recessed channel array transistor (RCAT) structures and method of formation are generally described. In one example, an electronic device includes a semiconductor substrate, a first fin coupled with the semiconductor substrate, the first fin comprising a first sourc... | 03/01/2011 |
| 7884418 | Semiconductor device and transistor A semiconductor device includes active areas which are insulatedly separated from each other by element-separation insulating films; a gate insulating film formed on each active area; a gate electrode which extends across the active area via the gate insulating film... | 02/08/2011 |
| 7851852 | Method of forming a low capacitance semiconductor device and structure therefor In one embodiment a transistor is formed with a gate structure having an opening in the gate structure. An insulator is formed on at least sidewalls of the opening and a conductor is formed on the insulator. ... | 12/14/2010 |
| 7829939 | MOSFET including epitaxial halo region A metal oxide semiconductor field effect transistor structure and a method for fabricating the metal oxide semiconductor field effect transistor structure provide for a halo region that is physically separated from a gate dielectric. The structure and the method als... | 11/09/2010 |
| 7808037 | High voltage device A high-voltage semiconductor device includes a silicon substrate having a main surface, a gate on the main surface of the silicon substrate, a source region in a portion of the silicon substrate proximate the main surface and a drain region in a portion of the silic... | 10/05/2010 |
| 7800165 | Semiconductor device and method for producing the same A semiconductor region having an upper surface and a side surface is formed on a substrate. A first impurity region is formed in an upper portion of the semiconductor region. A second impurity region is formed in a side portion of the semiconductor region. The resis... | 09/21/2010 |
| 7800166 | Recessed channel array transistor (RCAT) structures and method of formation Recessed channel array transistor (RCAT) structures and method of formation are generally described. In one example, an electronic device includes a semiconductor substrate, a first fin coupled with the semiconductor substrate, the first fin comprising a first sourc... | 09/21/2010 |
| 7795669 | Contact structure for FinFET device In accordance with an embodiment, a FinFET device includes: one or more fins, a dummy fin, a gate line, a gate contact landing pad, and a gate contact element. Each of the fins extends in a first direction above a substrate. The dummy fin extends in parallel with th... | 09/14/2010 |
| 7791131 | Semiconductor device and a method of manufacturing the same To reduce the size and improve the power added efficiency of an RF power module having an amplifier element composed of a silicon power MOSFET, the on resistance and feedback capacitance, which were conventionally in a trade-off relationship, are reduced simultaneou... | 09/07/2010 |
| 7786527 | Sub-lithographic gate length transistor using self-assembling polymers A semiconductor structure including at least one transistor located on a surface of a semiconductor substrate, wherein the at least one transistor has a sub-lithographic channel length, is provided. Also provided is a method to form such a semiconductor structure us... | 08/31/2010 |
| 7759728 | Depletable cathode low charge storage diode An integrated circuit device comprising a diode and a method of making an integrated circuit device comprising a diode are provided. The diode can comprise an island of a first conductivity type, a first region of a second conductivity type formed in the island, and... | 07/20/2010 |
| 7750396 | Semiconductor device and method for fabricating the same A semiconductor device includes: a semiconductor substrate; a source region and a drain region formed in the upper part of the semiconductor substrate so as to be spaced; a channel region formed in a part of the semiconductor substrate between the source region and ... | 07/06/2010 |
| 7737489 | Printed electronic device and transistor device and manufacturing method thereof An electronic device, e.g., a printed transistor device, comprises a substrate, a first conductive layer, a second conductive layer and a semiconductor layer. The substrate has a first platform and a second platform embossing on the surface thereof, and the first an... | 06/15/2010 |
| 7700998 | Semiconductor device and method for manufacturing the same A type semiconductor device includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type; a third semiconductor layer of the first conductivity type; a plurality of gate electrodes which are formed in... | 04/20/2010 |
| 7679131 | Semiconductor device, manufacturing method thereof, and electronic device A laser annealing method for obtaining a crystalline semiconductor film having a large grain size, and a method of manufacturing a semiconductor device using the crystalline semiconductor film, are provided. Using a shape change (convex portion or concave portion) o... | 03/16/2010 |
| 7667263 | Semiconductor structure including doped silicon carbon liner layer and method for fabrication thereof A semiconductor structure and related method for fabrication thereof includes a liner layer interposed between: (1) a pedestal shaped channel region within a semiconductor substrate; and (2) a source region and a drain region within a semiconductor material layer lo... | 02/23/2010 |
| 7655972 | Structure and method for MOSFET with reduced extension resistance The present invention provides a method in which a low-resistance connection between the MOS channel and silicided source/drain regions is provided that has an independence from the extension ion implant process as well as device overlap capacitance. The method of t... | 02/02/2010 |
| 7646057 | Gate structure with first S/D aside the first gate in a trench and the second gate with second S/D in the epitaxial below sides of the second gate on the first gate Disclosed is a semiconductor device. The semiconductor device includes a first gate formed in a trench of a semiconductor substrate, a first gate oxide layer on the semiconductor substrate including the first gate, a first epitaxial layer on the first gate oxide lay... | 01/12/2010 |
| 7638837 | Stress enhanced semiconductor device and methods for fabricating same A stress-enhanced semiconductor device is provided which includes a substrate having an inactive region and an active region, a first-type stress layer overlying at least a portion of the active region, and a second-type stress layer. The active region includes a fi... | 12/29/2009 |
| 7629643 | Independent n-tips for multi-gate transistors Independent n-tips for multi-gate transistors are generally described. In one example, an apparatus includes a semiconductor fin, one or more multi-gate pull down (PD) devices coupled with the semiconductor fin, the one or more PD devices having an n-tip dopant conc... | 12/08/2009 |
| 7598566 | Trench gate field effect devices The present invention provides a technique for accumulating minority carriers in the body region, that is, the intermediate region interposed between the top region and the deep region, and thus increasing the concentration of minority carriers in the intermediate r... | 10/06/2009 |
| 7586147 | Butted source contact and well strap A butted contact structure forming a source contact electrically connecting a voltage node and a well region and method for forming the same, the butted contact structure including an active region having a well region disposed adjacent an electrical isolation regio... | 09/08/2009 |
| 7557406 | Segmented pillar layout for a high-voltage vertical transistor In one embodiment, a transistor fabricated on a semiconductor die includes a first section of transistor segments disposed in a first area of the semiconductor die, and a second section of transistor segments disposed in a second area of the semiconductor die adjace... | 07/07/2009 |
| 7544994 | Semiconductor structure with multiple fins having different channel region heights and method of forming the semiconductor structure Disclosed are embodiments of a semiconductor structure with fins that are positioned on the same planar surface of a wafer and that have channel regions with different heights. In one embodiment the different channel region heights are accomplished by varying the ov... | 06/09/2009 |
