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| Number | Title | Issue Date |
| 8188536 | Memory device and manufacturing method and operating method thereof A memory device including a substrate, a plurality of conductive layers, a composite dielectric layer and a plurality of gates are provided. Wherein, the conductive layers are disposed on the substrate. The composite dielectric layer is disposed on the substrate and... | 05/29/2012 |
| 8183623 | Dual charge storage node memory device and methods for fabricating such device A dual node memory device and methods for fabricating the device are provided. In one embodiment the method comprises forming a layered structure with an insulator layer, a charge storage layer, a buffer layer, and a sacrificial layer on a semiconductor substrate. T... | 05/22/2012 |
| 8183622 | Flash memory device comprising bit-line contact region with dummy layer between adjacent contact holes A semiconductor device includes bit lines (12) that are provided in a semiconductor substrate (10) an ONO film (14) that is provided on the semiconductor substrate; word lines that are provided on the ONO film (14) and extend in a width d... | 05/22/2012 |
| 8178917 | Non-volatile semiconductor storage device having memory cells disposed three-dimensionally, and method of manufacturing the same A non-volatile semiconductor storage device includes a first layer and a second layer. The first layer includes: a plurality of first conductive layers extending in parallel to a substrate and laminated in a direction perpendicular to the substrate; a first insulati... | 05/15/2012 |
| 8178919 | Nonvolatile semiconductor memory device and method for manufacturing same A nonvolatile semiconductor memory device, includes: a stacked structural unit including electrode films alternately stacked with inter-electrode insulating films; first and second semiconductor pillars piercing the stacked structural unit; a connection portion semi... | 05/15/2012 |
| 8178918 | Charge trap type non-volatile memory device and method for fabricating the same There is provided a charge trap type non-volatile memory device and a method for fabricating the same, the charge trap type non-volatile memory device including: a tunnel insulation layer formed over a substrate; a charge trap layer formed over the tunnel insulation... | 05/15/2012 |
| 8174063 | Non-volatile semiconductor memory device with intrinsic charge trapping layer A non-volatile semiconductor memory device includes a substrate, a first gate formed on a first region of a surface of the substrate, a second gate formed on a second region of the surface of the substrate, a charge storage layer filled between the first gate and th... | 05/08/2012 |
| 8159019 | Semiconductor memory device with stacked gate including charge storage layer and control gate and method of manufacturing the same A semiconductor memory device includes a first active region, a second active region, a first element isolating region and a second element isolating region. The first active region is formed in a semiconductor substrate. The second active region is formed in the se... | 04/17/2012 |
| 8159018 | Non-volatile memory device A finFET-based non-volatile memory device on a semiconductor substrate includes source and drain regions, a fin body, a charge trapping stack and a gate. The fin body extends between the source and the drain region as a connection. The charge trapping stack covers a... | 04/17/2012 |
| 8148770 | Memory device with buried bit line structure A memory device includes a number of memory cells and a bit line structure coupled to a group of the memory cells. The bit line structure includes an upper portion having a first width, and a lower portion having a second width, where the first width is less than th... | 04/03/2012 |
| 8143666 | Semiconductor device with amorphous silicon monos memory cell structure and method for manufacturing thereof A semiconductor device with an amorphous silicon (a-Si) metal-oxide-nitride-oxide-semiconductor (MONOS) memory cell structure. The device includes a substrate, a dielectric layer overlying the substrate, and one or more source or drain regions embedded in the dielec... | 03/27/2012 |
| 8134201 | Semiconductor memory device provided with stacked layer gate including charge accumulation layer and control gate, and manufacturing method thereof A semiconductor memory device includes a memory cell transistor and a first MOS transistor. The memory cell transistor includes a first insulating film, a second insulating film, a control gate electrode, and a first diffusion layer. The first insulating film formed... | 03/13/2012 |
| 8134202 | Capacitorless one-transistor semiconductor memory device having improved data retention abilities and operation characteristics A capacitorless one transistor (1T) semiconductor device whose data storage abilities are increased and leakage current is reduced is provided. The capacitor-less 1T semiconductor device includes a buried insulating layer formed on a substrate, an active region form... | 03/13/2012 |
| 8129775 | Semiconductor device and method of manufacturing the same The semiconductor device has a stacked structure in which a tunnel oxide layer, a charge trapping layer, a blocking oxide layer, and a gate electrode are sequentially formed on a silicon substrate, wherein the blocking oxide layer includes a crystalline layer dispos... | 03/06/2012 |
| 8125019 | Electrically programmable resistor An electrically programmable resistor is presented. In one embodiment, a resistor includes a doped body within a substrate; a trapped charge region adjacent to the resistor, the resistance of the resistor controlled by an amount of trapped charge in the trapped char... | 02/28/2012 |
| 8125018 | Memory device having trapezoidal bitlines and method of fabricating same A memory device and a method of fabrication are provided. The memory device includes a semiconductor substrate and a charge trapping dielectric stack disposed over the semiconductor substrate. A gate electrode is disposed over the charge trapping dielectric stack, w... | 02/28/2012 |
| 8125020 | Non-volatile memory devices with charge storage regions A memory device includes a cell stack and a select gate formed adjacent to the cell stack. The cell stack includes a tunneling dielectric layer, a charge storage layer, a blocking dielectric layer, and a control gate. Applying a positive bias to the control gate, th... | 02/28/2012 |
| 8115249 | Nonvolatile semiconductor memory device and method for manufacturing the same In a nonvolatile semiconductor memory device, a tunnel insulating layer, a charge storage layer and a charge block layer are formed on a silicon substrate in this order, and a plurality of control gate electrodes are provided above the charge block layer. Moreover, ... | 02/14/2012 |
| 8110866 | Non-volatile memory device having asymmetric source/drain junction and method for fabricating the same Disclosed herein are non-volatile memory devices with asymmetric source/drain junctions and a method for fabricating the same. According to the method, a gate stack is formed on a semiconductor substrate, and impurity ions are implanted at a predetermined angle to f... | 02/07/2012 |
| 8106444 | Semiconductor device Provided is a semiconductor device including: source-drain regions formed on a silicon substrate with a channel forming region sandwiched therebetween; a word gate electrode formed on the channel forming region via a word gate insulating film not including a charge ... | 01/31/2012 |
| 8106443 | Non-volatile semiconductor memory device A non-volatile semiconductor device includes an n type well formed in a semiconductor substrate having a surface, the surface having a plurality of stripe shaped grooves and a plurality of stripe shaped ribs, a plurality of stripe shaped p type diffusion regions for... | 01/31/2012 |
| 8101990 | Semiconductor device A semiconductor device is provided, which includes a first insulating layer over a first substrate, a transistor over the first insulating layer, a second insulating layer over the transistor, a first conductive layer connected to a source region or a drain region o... | 01/24/2012 |
| 8089121 | Nonvolatile semiconductor memory device and method of manufacturing the same A nonvolatile semiconductor memory device includes a semiconductor layer as a channel, a conductive layer which is formed on a surface of the semiconductor layer with a first insulating layer and a second insulating layer interposed therebetween and functions as a c... | 01/03/2012 |
| 8089120 | Semiconductor memory device A semiconductor memory device includes: a semiconductor substrate; a stacked body with a plurality of conductive layers and a plurality of dielectric layers alternately stacked, the stacked body being provided on the semiconductor substrate; a semiconductor layer pr... | 01/03/2012 |
| 8084809 | Nonvolatile semiconductor memory device including pillars buried inside through holes In a nonvolatile semiconductor memory device, a stacked body is formed by alternately stacking dielectric films and conductive films on a silicon substrate and a plurality of through holes extending in the stacking direction are formed in a matrix configuration. A s... | 12/27/2011 |
| 8084810 | Fabrication method and structure of semiconductor non-volatile memory device A non-volatile semiconductor memory device with good write/erase characteristics is provided. A selection gate is formed on a p-type well of a semiconductor substrate via a gate insulator, and a memory gate is formed on the p-type well via a laminated film composed ... | 12/27/2011 |
| 8080843 | Nonvolatile memory devices and methods of forming the same Provided are nonvolatile memory devices and methods of forming nonvolatile memory devices. Nonvolatile memory devices include a device isolation layer that defines an active region in a substrate. Nonvolatile memory devices further include a first insulating layer, ... | 12/20/2011 |
| 8076715 | Dual-bit memory device having isolation material disposed underneath a bit line shared by adjacent dual-bit memory cells A dual-bit memory device is provided which includes trench isolation material disposed below a bit line that is shared by adjacent memory cells. The dual-bit memory device comprises a substrate, a first memory cell designed to store two bits of information, a second... | 12/13/2011 |
| 8072024 | Nonvolatile semiconductor memory device and method for manufacturing same A nonvolatile semiconductor memory device with a substrate. A plurality of dielectric films and electrode films are alternately stacked on the substrate and have a through hole penetrating in the stacking direction. A semiconductor pillar is formed inside the throug... | 12/06/2011 |
| 8063433 | Nonvolatile semiconductor memory device A memory cell includes an ONO film composed of a stacked film of a silicon nitride film SIN which is a charge trapping portion and oxide films BOTOX and TOPOX positioned under and over the silicon nitride film, a memory gate electrode MG over the ONO film, a source ... | 11/22/2011 |
| 8063434 | Memory transistor with multiple charge storing layers and a high work function gate electrode An embodiment of a semiconductor device includes a non-volatile memory transistor including an oxide-nitride-oxide (ONO) dielectric stack on a surface of a semiconductor substrate, the ONO dielectric stack comprising a multilayer charge storage layer including a sil... | 11/22/2011 |
| 8063436 | Memory cells configured to allow for erasure by enhanced F-N tunneling of holes from a control gate to a charge trapping material Memory cells including a control gate, a charge trapping material, and a charge blocking material between the control gate and the charge trapping material. The charge blocking material is configured to allow for erasure of the memory cell by enhanced F-N tunneling ... | 11/22/2011 |
| 8063435 | Semiconductor memory and method for manufacturing the same A semiconductor memory in which a gate insulating film (tunnel insulating film) in a memory cell provides higher operational reliability. The semiconductor memory includes an insulating film 3 between a silicon substrate 1 and a gate electrode 4... | 11/22/2011 |
| 8058681 | Nonvolatile semiconductor memory element, nonvolatile semiconductor memory, and method for operating nonvolatile semiconductor memory element According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory element including: a semiconductor substrate including: a source region; a drain region; and a channel region; a lower insulating film that is formed on the channel... | 11/15/2011 |
| 8053826 | Non-volatile semiconductor memory device and method of manufacturing the same The charge retention characteristics of a non-volatile memory, particularly, a MONOS-type non-volatile memory is improved. In a non-volatile memory cell including a tunnel silicon oxide film (107), a silicon nitride film (104) serving as a charge stora... | 11/08/2011 |
| 8049269 | Non-volatile memory device and method of manufacturing the same In a non-volatile memory device, active fin structures extending in a first direction may be formed on a substrate. A tunnel insulating layer may be formed on surfaces of the active fin structures and bottom surfaces of trenches that may be defined by the active fin... | 11/01/2011 |
| 8044454 | Non-volatile memory device A non-volatile memory device having a SONOS structure and a manufacturing method thereof, where a conductive layer is formed between a charge trap layer and a blocking insulation layer of the SONOS structure. Therefore, when a voltage is applied to a gate, the condu... | 10/25/2011 |
| 8044452 | Semiconductor device and method for manufacturing the same The present invention provides a high-quality semiconductor device in which deterioration in transistor characteristics and an increase in interface layer due to a gate insulating film are suppressed, and a method for manufacturing the same. In the present invention... | 10/25/2011 |
| 8044455 | Semiconductor device and method of manufacturing the same A step is provided between a substrate surface of a select gate and a substrate surface of a memory gate. When the substrate surface of the select gate is lower than the substrate surface of the memory gate, electrons in a channel upon writing obliquely flow in the ... | 10/25/2011 |
| 8044453 | Non-volatile memory device with a charge trapping layer A non-volatile memory device includes field insulating layer patterns on a substrate to define an active region of the substrate, upper portions of the field insulating layer patterns protruding above an upper surface of the substrate, a tunnel insulating layer on t... | 10/25/2011 |
