Did You Know...
...that the video game, Pong, was invented by a guy who graduated at the bottom of his engineering class? Nolan Bushnell spent more time running the games at a local amusement park than he did on his studies at the University of Utah. His dreams of working for Disney's amusement empire were dashed when the company wouldn't hire him. Taking a boring job, Nolan daydreamed about electronic versions of popular games. He invented Pong, the first video game, and went on to found Atari Co.
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| Number | Title | Issue Date |
| 7791129 | Semiconductor device and method of producing the same including a charge accumulation layer with differing charge trap surface density There is provided a trap memory device suppresses electric charges from flowing from the outside into a charge accumulation region and accumulated electric charges from diffusing to the outside or flowing out due to a defect. A gate conductor 6 is formed thro... | 09/07/2010 |
| 7671402 | Solid-state imaging devices A solid-state imaging device includes: a substrate; a photoelectric transducer that is provided within the substrate and generates light-generated charge in accordance with incident light; a floating diffusion that retains the light-generated charge generated from t... | 03/02/2010 |
| 7544992 | Illuminating efficiency-increasable and light-erasable embedded memory structure An illuminating efficiency-increasable and light-erasable embedded memory structure including a substrate, a memory device, many dielectric layers, many cap layers and at least three metal layers is described. The substrate includes a memory region and a core circui... | 06/09/2009 |
| 7538383 | Two-bit memory cell having conductive charge storage segments and method for fabricating same According to one exemplary embodiment, a two-bit memory cell includes a gate stack situated over a substrate, where the gate stack includes a charge-trapping layer. The charge-trapping layer includes first and second conductive segments and a nitride segment, where ... | 05/26/2009 |
| 7394127 | Non-volatile memory device having a charge storage oxide layer and operation thereof A non-volatile memory device includes a pair of source/drain regions disposed in a semiconductor substrate, having a channel region between them. A charge storage oxide layer is disposed on the channel region and overlaps part of each of the pair of source/drain reg... | 07/01/2008 |
| 7391078 | Non-volatile memory and manufacturing and operating method thereof A non-volatile memory is provided. A substrate having a plurality of trenches and a plurality of select gates is provided. The trenches are arranged in parallel and extend in a first direction. Each of the select gates is disposed on the substrate between two adjace... | 06/24/2008 |
| 7382015 | Semiconductor device including an element isolation portion having a recess A non-volatile semiconductor memory device, which is intended to prevent data destruction by movements of electric charges between floating gates and thereby improve the reliability, includes element isolation/insulation films buried into a silicon substrate to isol... | 06/03/2008 |
| 7352028 | Solid-state imaging devices A solid-state imaging device includes: a substrate; a photoelectric transducer that is provided within the substrate and generates light-generated charge in accordance with incident light; a floating diffusion that retains the light-generated charge generated from t... | 04/01/2008 |
| 7323741 | Semiconductor nonvolatile memory device A low cost semiconductor nonvolatile memory device capable of high speed programming, using an inversion layer as the wiring, and a manufacturing method for that device. The semiconductor memory device includes an auxiliary electrode at a position between and in par... | 01/29/2008 |
| 7300888 | Methods of manufacturing integrated circuit devices having an encapsulated insulation layer An integrated circuit device is manufactured by forming an insulating layer on a substrate. A capping layer is formed on the insulating layer and both the capping layer and the insulating layer are patterned. Insulating spacers are formed on sidewalls of the insulat... | 11/27/2007 |
| 7271029 | Method of forming a package-ready light-sensitive integrated circuit A package-ready light-sensitive integrated circuit and process for preparing a light-sensitive semiconductor substrate for packaging that provide for a reduced exposure of a light-sensitive integrated circuit to light. The package-ready light-sensitive integrated ci... | 09/18/2007 |
| 7253468 | Flash memory and methods of fabricating the same Flash memory and methods of fabricating the same are disclosed. An illustrated example flash memory includes a first source formed within a semiconductor substrate; an epitaxial layer formed on an upper surface of the semiconductor substrate; an opening formed withi... | 08/07/2007 |
| 7208794 | High-density NROM-FINFET Semiconductor memory having memory cells, each including first and second conductively-doped contact regions and a channel region arranged between the latter, formed in a web-like rib made of semiconductor material and arranged one behind the other in this sequence ... | 04/24/2007 |
| 7202524 | Nonvolatile memory device and method of manufacturing the same A nonvolatile memory device is provided which includes a floating gate having a lower portion formed in a trench defined in a surface of a substrate and an upper portion protruding above the surface of the substrate from the lower portion. A gate insulating layer is... | 04/10/2007 |
| 7198967 | Active matrix type semiconductor display device There is provided an active matrix type semiconductor display device which realizes low power consumption and high reliability. In the active matrix type semiconductor display device of the present invention, a counter electrode is divided into two, different potent... | 04/03/2007 |
| 7187043 | Memory function body, particle forming method therefor and, memory device, semiconductor device, and electronic equipment having the memory function body A memory function body has a medium interposed between a first conductor (e.g., a conductive substrate) and a second conductor (e.g., an electrode) and consisting of a first material (e.g., silicon oxide or silicon nitride). The medium contains particles. Each parti... | 03/06/2007 |
| 7183662 | Memory devices with memory cell transistors having gate sidewell spacers with different dielectric properties A memory device, such as a DRAM, SRAM or non-volatile memory device, includes a substrate, a gate electrode disposed on the substrate, and source and drain regions in the substrate adjacent respective first and second sidewalls of the gate electrode. First and secon... | 02/27/2007 |
| 7160775 | Method of discharging a semiconductor device In one embodiment, a method for discharging a semiconductor device includes providing a semiconductor substrate, forming a hole blocking dielectric layer over the semiconductor substrate, forming nanoclusters over the hole blocking dielectric layer, forming a charge... | 01/09/2007 |
| 7157742 | Integrated circuit device An integrally packaged optronic integrated circuit device (310) including an integrated circuit die (322) containing at least one of a radiation emitter and radiation receiver and having top and bottom surfaces formed of electrically insulative and mec... | 01/02/2007 |
| 7148529 | Semiconductor package A semiconductor package includes (a) an interposer, (b) a wiring layer containing conductors formed adjacent to each other at intervals that cause no short circuit among the conductors, the wiring layer covering a given area of the interposer, to block light from pa... | 12/12/2006 |
| 7145193 | Semiconductor integrated circuit device and process for manufacturing the same In a peripheral circuit region of a DRAM, two connection holes, for connecting a first layer line and a second layer line electrically are opened separately in two processes. After forming the connection holes, plugs are formed in the respective connection holes. | 12/05/2006 |
| 7122857 | Multi-level (4state/2-bit) stacked gate flash memory cell A method is provided for forming a highly dense stacked gate flash memory cell with a structure having multi floating gates that can assume 4 states and, therefore, store 2 bits at the same time. This is accomplished by providing a semiconductor substrate having gat... | 10/17/2006 |
| 7119393 | Transistor having fully-depleted junctions to reduce capacitance and increase radiation immunity in an integrated circuit A floating-gate transistor for an integrated circuit is formed on a p-type substrate. An n-type region is disposed over the p-type substrate. A p-type region is disposed over the n-type region. Spaced apart n-type source and drain regions are disposed in the p-type ... | 10/10/2006 |
| 7115939 | Floating gate transistor with horizontal gate layers stacked next to vertical body Vertical body transistors with adjacent horizontal gate layers are used to form a memory array in a high density flash electrically erasable and programmable read only memory (EEPROM) or a logic array in a high density field programmable logic array (FPLA). The tran... | 10/03/2006 |
| 7098107 | Protective layer in memory device and method therefor A method for protecting a non-volatile memory device, the method including forming a non-volatile memory device including a polycide structure formed over a non-conducting charge trapping layer, and forming a protective layer over at least a portion of the polycide ... | 08/29/2006 |
| 7078749 | Memory structure having tunable interlayer dielectric and method for fabricating same According to one embodiment, a memory structure comprises a substrate having a channel region situated between a source region and a drain region. The memory structure further comprises a gate layer formed over the channel region of the substrate, and a tunable inte... | 07/18/2006 |
| 7067414 | Low k interlevel dielectric layer fabrication methods A low k inter-level dielectric layer fabrication method includes providing a substrate having integrated circuitry at least partially formed thereon. An oxide-comprising inter-level dielectric layer including carbon and having a dielectric constant no greater than 3... | 06/27/2006 |
| 7057928 | System and method for erasing high-density non-volatile fast memory A system and method for erasing a high-density non-volatile fast memory is presented. In one embodiment the high-density non-volatile fast memory is a modified flash memory having modified flash cells. One embodiment of the system comprises ultra-violet (UV) light w... | 06/06/2006 |
| 7018898 | Non-volatile two transistor semiconductor memory cell and method for producing the same The invention relates to a nonvolatile two-transistor semiconductor memory cell and an associated fabrication method, source and drain regions (2) for a selection transistor (AT) and a memory transistor (ST) being formed in a substrate (1). The memory ... | 03/28/2006 |
| 6969654 | Flash NVROM devices with UV charge immunity A method of preventing UV charging of flash NVROM cells during fabrication and a device thereby formed. During device fabrication, a UV blocking layer is deposited over the floating gates. The UV blocking layer substantially blocks UV from entering the gate regions ... | 11/29/2005 |
| 6957905 | Solid state light source A light source includes a housing, an LED array of individual LED elements mounted in the housing, and a controller mounted in the housing and coupled to the LED array. The controller sequentially, intermittently pulses the LED elements of the LED array. The control... | 10/25/2005 |
| 6946702 | Resistance random access memory The present invention provides a resistance random access memory structure, including a plurality of word lines in a substrate, a plurality of reset lines coupled to the word lines, a dielectric layer on the substrate, a plurality of memory units in the dielectric l... | 09/20/2005 |
| 6939799 | Method of forming a field effect transistor and methods of forming integrated circuitry A method of forming integrated circuitry includes forming a field effect transistor gate over a substrate. The gate comprises polysilicon conductively doped with a conductivity enhancing impurity of a first type and a conductive diffusion barrier layer to diffusion ... | 09/06/2005 |
| 6930923 | Flash memory capable of utilizing one driving voltage output circuit to drive a plurality of word line drivers A flash memory capable of utilizing one driving voltage output circuit to drive a plurality of word line drivers. The flash memory has a row driver for driving a predetermined word line to approach a predetermined voltage level. The row driver has a plurality of wor... | 08/16/2005 |
| 6870216 | Stack gate with tip vertical memory and method for fabricating the same A stacked gate vertical flash memory and a fabrication method thereof. The stacked gate vertical flash memory comprises a semiconductor substrate with a trench, a source conducting layer formed on the bottom of the trench, an insulating layer formed on the source co... | 03/22/2005 |
| 6815762 | Semiconductor integrated circuit device and process for manufacturing the same including spacers on bit lines In a process for manufacturing a semiconductor integrated circuit device having a MISFET, in order that a shallow junction between the source/drain of the MISFET and a semiconductor substrate may be realized by reducing the number of heat treatment steps, all conduc... | 11/09/2004 |
| 6803319 | Process for optically erasing charge buildup during fabrication of an integrated circuit A process for optically reducing charge build-up in an integrated circuit includes exposing the integrated circuit or portions thereof to a broadband radiation source. The process effectively reduces charge buildup that occurs in the manufacture of integrated circui... | 10/12/2004 |
| 6762068 | Transistor with variable electron affinity gate and methods of fabrication and use A CMOS-compatible FET has a reduced electron affinity polycrystalline or microcrystalline SiC gate that is electrically isolated (floating) or interconnected. The SiC material composition is selected to establish the barrier energy between the SiC gate and a gate in... | 07/13/2004 |
| 6713812 | Non-volatile memory device having an anti-punch through (APT) region A memory device (70) that uses a non-volatile storage element (38), such as nitride, has reduced read disturb, which is the problem of tending to increase the threshold voltage of a memory device (70) during a read. To reduce this effect, the me... | 03/30/2004 |
| 6635943 | Method and system for reducing charge gain and charge loss in interlayer dielectric formation A method and system for insulating a lower layer of a semiconductor device from an upper layer of the semiconductor device is disclosed. The method and system include providing an interlayer dielectric on the lower layer. The interlayer dielectric is capa... | 10/21/2003 |
