Did You Know...
...that to encourage use of his new invention, the shopping cart, market owner Sylvan Goldman hired fake shoppers to push the carts around his store in Oklahoma City? Seems his customers were reluctant to give up their hand-carried baskets.
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| Number | Title | Issue Date |
| 8134200 | Nonvolatile semiconductor memory including a gate insulating film and an inter-gate insulating film A nonvolatile semiconductor memory of an aspect of the present invention includes a memory cell including, a charge storage layer on a gate insulating film, a multilayer insulator on the charge storage layer, and a control gate electrode on the multilayer insulator,... | 03/13/2012 |
| 7884416 | Semiconductor integrated circuit A semiconductor integrated circuit according to an example of the present invention includes a semiconductor substrate, an element isolation insulating layer formed in a surface region of the semiconductor substrate, and first and second MIS type devices isolated fr... | 02/08/2011 |
| 7872298 | Split-gate type memory device Performance and reliability of a semiconductor device including a non-volatile memory are improved. A memory cell of the non-volatile memory includes, over an upper portion of a semiconductor substrate, a select gate electrode formed via a first dielectric film and ... | 01/18/2011 |
| 7868375 | Split gate non-volatile flash memory cell having a floating gate, control gate, select gate and an erase gate with an overhang over the floating gate, array and method of manufacturing An improved split gate non-volatile memory cell is made in a substantially single crystalline substrate of a first conductivity type, having a first region of a second conductivity type, a second region of the second conductivity type, with a channel region between ... | 01/11/2011 |
| 7863673 | Non-volatile memory device and method of operating the same A non-volatile memory device includes a semiconductor substrate, first and second control gates, and first and second charge storage patterns. The semiconductor substrate includes a protruding active pin having a source region, a drain region and a channel region lo... | 01/04/2011 |
| 7851846 | Non-volatile memory cell with buried select gate, and method of making same A memory device, and method of making the same, in which a trench is formed into the surface of a semiconductor substrate. Source and drain regions define a channel region there between. The drain is formed under the trench. The channel region includes a first porti... | 12/14/2010 |
| 7728378 | Nonvolatile semiconductor memory device, manufacturing method thereof and method of programming information into the memory device A nonvolatile semiconductor memory device capable of improving injection efficiency and simplifying manufacturing process is provided. The device comprises a memory cell having second conductive type of first impurity diffusion area and second impurity diffusion are... | 06/01/2010 |
| 7687849 | Method for manufacturing semiconductor integrated circuit device Disclosed is a technique for reducing the leak current by reducing contamination of metal composing a polymetal gate of a MISFET. Of a polycrystalline silicon film, a WN film, a W film, and a cap insulating film formed on a gate insulating film on a p-type well (sem... | 03/30/2010 |
| 7586146 | Non-volatile memory and method of fabricating same In one embodiment, a semiconductor device includes a semiconductor substrate having a first junction region and a second junction region. An insulated floating gate is disposed on the substrate. The floating gate at least partially overlaps the first junction region... | 09/08/2009 |
| 7547941 | NAND non-volatile two-bit memory and fabrication method A NAND non-volatile two-bit memory cell comprises a cell stack and two select stacks disposed on an active area of a substrate. Each select stack is respectively disposed on a side of the cell stack with a sidewall between the cell stack and a respective select stac... | 06/16/2009 |
| 7442989 | Nonvolatile semiconductor memory device and method of manufacturing thereof This invention is intended to improve reliability of a nonvolatile semiconductor memory device and reduces a memory cell size of the nonvolatile semiconductor memory device. A memory cell which includes source/drain diffusion layers in a p-type well formed in a sili... | 10/28/2008 |
| 7436020 | Flash memory with metal-insulator-metal tunneling program and erase The flash memory cell comprises a sense transistor that has a pair of source/drain lines and a control gate. A coupling metal-insulator-metal capacitor is created between the control gate and a read wordline. A tunneling metal-insulator-metal capacitor is created be... | 10/14/2008 |
| 7436707 | Flash memory cell structure and operating method thereof A flash memory cell structure has a substrate, a select gate, a first-type doped region, a shallow second-type doped region, a deep second-type doped region, and a doped source region. The substrate has a stacked gate. The select gate is formed on the substrate and ... | 10/14/2008 |
| RE40486 | Self-aligned non-volatile memory cell Disclosed is a self-aligned non-volatile memory cell including a small sidewall spacer electrically coupled and being located next to a main floating gate region. Both the small sidewall spacer and the main floating gate region are formed on a substrate and both for... | 09/09/2008 |
| 7419865 | Methods of forming memory circuitry The invention includes methods of forming memory circuitry. In one implementation, a semiconductor substrate includes a pair of word lines having a bit node received therebetween. A bit node contact opening is formed within insulative material over the bit node. Sac... | 09/02/2008 |
| 7414285 | Nonvolatile semiconductor memory device A nonvolatile semiconductor memory device includes a first insulating film provided on a surface of a semiconductor substrate, a charge accumulation layer provided on the first insulating film, a second insulating film provided above the charge accumulation layer an... | 08/19/2008 |
| 7414283 | Semiconductor device A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which ... | 08/19/2008 |
| 7397080 | Non-volatile memory A non-volatile memory including at least a substrate, a memory cell and source/drain regions is provided. The memory cell is disposed on the substrate and includes at least a first memory unit and a second memory unit. Wherein, the first memory unit, from the substr... | 07/08/2008 |
| 7391078 | Non-volatile memory and manufacturing and operating method thereof A non-volatile memory is provided. A substrate having a plurality of trenches and a plurality of select gates is provided. The trenches are arranged in parallel and extend in a first direction. Each of the select gates is disposed on the substrate between two adjace... | 06/24/2008 |
| 7385245 | Low power memory subsystem with progressive non-volatility The memory system is comprised of a plurality of memory arrays that are coupled to a processor. The memory arrays are comprised of non-volatile memory cells that have read/write speeds and charge retention times that are different from the other memory arrays of the... | 06/10/2008 |
| 7382015 | Semiconductor device including an element isolation portion having a recess A non-volatile semiconductor memory device, which is intended to prevent data destruction by movements of electric charges between floating gates and thereby improve the reliability, includes element isolation/insulation films buried into a silicon substrate to isol... | 06/03/2008 |
| 7372734 | Methods of operating electrically alterable non-volatile memory cell A nonvolatile memory cell is provided. The memory cell includes a storage transistor and an injector in a well of an n-type conductivity. The well is formed in a semiconductor substrate of a p-type conductivity. The storage transistor comprises a source, a drain, a ... | 05/13/2008 |
| 7370166 | Secure portable storage device In one embodiment of the present invention, a secure storage system includes a removable storage device having a secure storage area for storage of secure data and a public storage area and device port for coupling the removable storage device to a host, the removab... | 05/06/2008 |
| 7368346 | Method for forming gate structure in flash memory device Device isolation insulation layers passing through an insulation layer and a substrate, are formed, and a portion of them is removed. The insulation layer is removed. A gate oxide layer and a first conductive layer sequentially formed over the device isolation insul... | 05/06/2008 |
| 7365387 | Gate-coupled EPROM cell for printhead An EPROM cell in a printhead control circuit for an inkjet printer, having exactly one polysilicon layer and a conductive layer disposed above the polysilicon layer, includes a control transistor and an EPROM transistor. The control and EPROM transistors each have f... | 04/29/2008 |
| 7365383 | Method of forming an EPROM cell and structure therefor An EPROM cell includes a control gate and a control transistor. A portion of the control transistor is formed as a portion of the control gate. ... | 04/29/2008 |
| 7358134 | Split gate flash memory cell and manufacturing method thereof A split gate flash memory cell includes a substrate having a device isolation structure; a selective gate structure disposed on the substrate; an interlayer dielectric layer having an opening disposed on the substrate, wherein the opening exposes a portion of the se... | 04/15/2008 |
| 7355237 | Shield plate for limiting cross coupling between floating gates A memory system is disclosed that includes a set of non-volatile storage elements. Each of said non-volatile storage elements includes source/drain regions at opposite sides of a channel in a substrate and a floating gate stack above the channel. The memory system a... | 04/08/2008 |
| 7352620 | Non-volatile semiconductor device and method for automatically recovering erase failure in the device A spare sector is in a blank state beforehand. Each time the erasing is carried out in practical use, the number of erase pulses is counted or the presence/absence of overcurrent flowing when the erase pulse is being applied is monitored. A regular sector having lon... | 04/01/2008 |
| 7348618 | Flash memory cell having reduced floating gate to floating gate coupling According to an embodiment of the invention, a flash memory cell includes a first gate stack and a second gate stack having a film deposited across the gap between the first and second gate stacks so that the film creates a void between the first and second gate sta... | 03/25/2008 |
| 7339230 | Structure and method for making high density mosfet circuits with different height contact lines Embodiments herein present a structure, method, etc. for making high density MOSFET circuits with different height contact lines. The MOSFET circuits include a contact line, a first gate layer situated proximate the contact line, and at least one subsequent gate lay... | 03/04/2008 |
| 7340581 | Method of writing data to non-volatile memory According to a first aspect of the invention, there is provided a controller connected to a non-volatile memory and including a volatile memory, wherein the controller maintains lists in volatile memory of blocks in the non-volatile memory allocated for storage of l... | 03/04/2008 |
| 7335940 | Flash memory and manufacturing method thereof A method for manufacturing flash memory is provided. A tunneling dielectric layer, a conductive layer and a patterned mask layer that exposes a portion of the conductive layer are formed on a substrate. An oxide layer is formed on the exposed conductive layer so tha... | 02/26/2008 |
| 7326992 | Nonvolatile memory cell with multiple floating gates formed after the select gate In a memory cell (110) having multiple floating gates (160), the select gate (140) is formed before the floating gates. In some embodiments, the memory cell also has control gates (170) formed after the select gate. Substrate isolation re... | 02/05/2008 |
| 7323740 | Single chip data processing device with embedded nonvolatile memory and method thereof A device is described comprising a substrate of a first conductivity type having a first dopant concentration, a first well formed in the substrate, a second well of the first conductivity type formed in the substrate and being deeper than the first well, the second... | 01/29/2008 |
| 7323743 | Floating gate A floating gate and fabrication method thereof. A semiconductor substrate is provided, on which an oxide layer, a first conducting layer, and a patterned hard mask layer having an opening are sequentially formed. A spacer is formed on the sidewall of the opening. A ... | 01/29/2008 |
| 7321511 | Semiconductor device and method for controlling operation thereof A semiconductor device includes a semiconductor substrate, word lines, global bit lines, and inversion gates that form inversion layers serving as local bit lines in the semiconductor substrate. The inversion layers are electrically connected to the global bit lines... | 01/22/2008 |
| 7312495 | Split gate multi-bit memory cell A multi-bit memory cell (200) with a control gate (220) for controlling a middle portion of a channel region (208) provides improved operation including faster programming at smaller voltages and currents. The memory cell (200) includes a... | 12/25/2007 |
| 7306990 | Information storage element, manufacturing method thereof, and memory array An information memory device capable of reading and writing of information by mechanical operation of a floating gate layer, in which a gate insulation film has a cavity (6), and a floating gate layer (5) having two stable deflection states in the cavi... | 12/11/2007 |
| 7307889 | Semiconductor memory A semiconductor memory is achieved which allows a reduction in the area of a memory array block without reducing the gate widths of floating gates. A plurality of select gates extend in straight lines in the X direction. Between the upper- and lower-side select gate... | 12/11/2007 |
