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| Number | Title | Issue Date |
| 8188535 | Nonvolatile semiconductor memory device and manufacturing method thereof An object is to suppress reading error even in the case where writing and erasing are repeatedly performed. Further, another object is to reduce writing voltage and erasing voltage while increase in the area of a memory transistor is suppressed. A floating gate and ... | 05/29/2012 |
| 8120092 | Semiconductor memory device and manufacturing method therefor First gate electrodes of memory cell transistors are formed in series with each other on a semiconductor substrate. A second gate electrode of a first selection transistor is formed adjacent to one end of the first electrodes. A third gate electrode of a second sele... | 02/21/2012 |
| 8093649 | Flash memory cell A flash memory cell includes a substrate, a source, a drain, a first oxide, a second oxide, a floating gate and a control gate. The source and a drain are formed in the substrate separately, and are doped with N-type ions. The first oxide is formed on the substrate.... | 01/10/2012 |
| 8058680 | Nonvolatile semiconductor memory with erase gate and its manufacturing method A nonvolatile semiconductor memory device includes a semiconductor substrate, a select gate formed above the semiconductor substrate, a floating gate formed above the semiconductor substrate and an erase gate positioned lower than an upper surface of the floating ga... | 11/15/2011 |
| 8013382 | NAND flash memory and method of manufacturing the same A semiconductor memory in which each memory cell in a NAND flash memory includes a columnar floating gate formed on an element region with a gate insulating film interposed between the floating gate and the element region, diffusion layers formed at portions of the ... | 09/06/2011 |
| 7968934 | Memory device including a gate control layer An integrated memory device, an integrated memory chip and a method for fabricating an integrated memory device is disclosed. One embodiment provides at least one integrated memory device with a drain, a source, a floating gate, a selection gate and a control gate, ... | 06/28/2011 |
| 7923769 | Split gate non-volatile memory cell with improved endurance and method therefor A non-volatile memory cell including a substrate in which is formed a source region and a drain region defining a channel region between the source region and the drain region is provided. The non-volatile memory cell further includes a select gate structure overlyi... | 04/12/2011 |
| 7893483 | Neuron device A neuron device includes: a semiconductor layer; source and drain regions formed in the semiconductor layer at a distance from each other; a protection film formed on an upper face of the semiconductor layer; a channel region formed in the semiconductor layer betwee... | 02/22/2011 |
| 7863672 | Non-volatile memory device and method of fabricating the same Provided are a non-volatile memory device that may expand to a stacked structure and may be more easily highly integrated and an economical method of fabricating the non-volatile memory device. The non-volatile memory device may include at least one semiconductor co... | 01/04/2011 |
| 7838922 | Electronic device including trenches and discontinuous storage elements An electronic device can include a substrate including a trench having a bottom and a first wall. The electronic device can also include a first gate electrode within the trench and adjacent to the first wall and overlying the bottom of the trench, a second gate ele... | 11/23/2010 |
| 7834390 | Nonvolatile semiconductor memory device and method of manufacturing the same A nonvolatile semiconductor memory device has: a semiconductor substrate; a control gate and a floating gate that are formed side by side on a gate insulating film on a channel region in the semiconductor substrate; an erase gate facing an upper surface of the float... | 11/16/2010 |
| 7829934 | Flash memory device having resistivity measurement pattern and method of forming the same A flash memory device has a resistivity measurement pattern and method of forming the same. A trench is formed in an isolation film in a Self-Aligned Floating Gate (SAFG) scheme. The trench is buried to form a resistivity measurement floating gate. This allows the r... | 11/09/2010 |
| 7808034 | Non-volatile memory cell with fully isolated substrate as charge storage In a non-volatile memory cell, charge is stored in a fully isolated substrate or floating bulk that forms a storage capacitor with a first poly strip and includes a second poly strip defining a control gate and a third poly strip coupled to a read transistor gate. | 10/05/2010 |
| 7800161 | Flash NAND memory cell array with charge storage elements positioned in trenches NAND arrays of memory cells are described, as well as methods of forming and using them. Memory cell charge storage devices, such as conductive floating gates, are oriented vertically in trenches, with control gates positioned both in the trenches between charge sto... | 09/21/2010 |
| 7777271 | System and method for providing low cost high endurance low voltage electrically erasable programmable read only memory A system and method are disclosed for increasing the reliability of a channel erase procedure in an electrically erasable programmable read only memory (EEPROM) memory cell. A memory cell of the present invention comprises a program gate, a control gate, and a float... | 08/17/2010 |
| 7714378 | Nonvolatile semiconductor integrated circuit devices and fabrication methods thereof In a method for manufacturing a semiconductor device, an oxide layer, a first polysilicon layer, and a second polysilicon layer are sequentially provided on a substrate. A first hard mask pattern is provided on the second polysilicon layer. The oxide layer, the firs... | 05/11/2010 |
| 7692235 | Nonvolatile semiconductor memory device including memory cells formed to have double-layered gate electrodes A nonvolatile semiconductor memory device includes a plurality of floating gate electrodes respectively formed above a semiconductor substrate with first insulating films disposed therebetween, and a control gate electrode formed above the plurality of floating gate... | 04/06/2010 |
| 7655970 | Single poly non-volatile memory device with inversion diffusion regions and methods for operating the same A non-volatile memory device comprises a substrate with the dielectric layer formed thereon. A control gate and a floating gate are then formed next to each other on top of the dielectric layer separated by a gap. Accordingly, a non-volatile memory device can be con... | 02/02/2010 |
| 7642595 | Nonvolatile semiconductor memory and method of fabrication thereof There are provided a nonvolatile semiconductor memory of a structure in which electric signals from peripheral circuits are reliably transferred to control gates via word lines even if contact holes cannot be opened accurately above the word lines, and a method of f... | 01/05/2010 |
| 7638834 | Flash memory cell arrays having dual control gates per memory cell charge storage element A flash NAND type EEPROM system with individual ones of an array of charge storage elements, such as floating gates, being capacitively coupled with at least two control gate lines. The control gate lines are preferably positioned between floating gates to be couple... | 12/29/2009 |
| 7602008 | Split gate non-volatile memory devices and methods of forming the same Non-volatile memory devices and methods for fabricating non-volatile memory devices are disclosed. More specifically, split gate memory devices are provided having frameworks that provide increased floating gate coupling ratios, thereby enabling enhanced programming... | 10/13/2009 |
| 7492000 | Self-aligned split-gate nonvolatile memory structure and a method of making the same Provided are non-volatile split-gate memory cells having self-aligned floating gate and the control gate structures and exemplary processes for manufacturing such memory cells that provide improved dimensional control over the relative lengths and separation of the ... | 02/17/2009 |
| 7449746 | EEPROM with split gate source side injection Novel memory cells utilize source-side injection, allowing very small programming currents. If desired, to-be-programmed cells are programmed simultaneously while not requiring an unacceptably large programming current for any given programming operation. In one emb... | 11/11/2008 |
| 7442988 | Semiconductor devices and methods of fabricating the same Disclosed is a semiconductor device and method of fabricating the same. The device is disposed on a substrate, including a fin constructed with first and second sidewalls, a first gate line formed in the pattern of spacer on the first sidewall of the fin, and a seco... | 10/28/2008 |
| 7442985 | Semiconductor memory device having memory cell section and peripheral circuit section and method of manufacturing the same An element isolating region for separating an element region of a semiconductor layer is formed in a peripheral circuit section of a semiconductor memory device, and a first conductive layer is formed with the element region with a first insulating film interposed t... | 10/28/2008 |
| RE40486 | Self-aligned non-volatile memory cell Disclosed is a self-aligned non-volatile memory cell including a small sidewall spacer electrically coupled and being located next to a main floating gate region. Both the small sidewall spacer and the main floating gate region are formed on a substrate and both for... | 09/09/2008 |
| 7391078 | Non-volatile memory and manufacturing and operating method thereof A non-volatile memory is provided. A substrate having a plurality of trenches and a plurality of select gates is provided. The trenches are arranged in parallel and extend in a first direction. Each of the select gates is disposed on the substrate between two adjace... | 06/24/2008 |
| 7382015 | Semiconductor device including an element isolation portion having a recess A non-volatile semiconductor memory device, which is intended to prevent data destruction by movements of electric charges between floating gates and thereby improve the reliability, includes element isolation/insulation films buried into a silicon substrate to isol... | 06/03/2008 |
| 7378706 | Semiconductor device and method of manufacturing the same An insulating film provided below a floating gate electrode includes a first insulating film located at both end portions below the floating gate electrode, and a second insulating film sandwiched between the first insulating films and located in a middle portion be... | 05/27/2008 |
| 7369436 | Vertical NAND flash memory device Memory devices, arrays, and strings are included that facilitate the use of vertical floating gate memory cells in NAND architecture memory strings, arrays, and devices. NAND Flash memory strings, arrays, and devices, include vertical Flash memory cells to form NAND... | 05/06/2008 |
| 7364997 | Methods of forming integrated circuitry and methods of forming local interconnects In one implementation, field oxide is grown within bulk semiconductive material in a first circuitry area and not over immediately adjacent bulk semiconductive material in a second circuitry area. The field oxide is etched from the first circuitry area. After the et... | 04/29/2008 |
| 7355237 | Shield plate for limiting cross coupling between floating gates A memory system is disclosed that includes a set of non-volatile storage elements. Each of said non-volatile storage elements includes source/drain regions at opposite sides of a channel in a substrate and a floating gate stack above the channel. The memory system a... | 04/08/2008 |
| 7352026 | EEPROM cell and EEPROM device with high integration and low source resistance and method of manufacturing the same Provided are an EEPROM cell, an EEPROM device, and methods of manufacturing the EEPROM cell and the EEPROM device. The EEPROM cell is formed on a substrate including a first region and a second region. A first EEPROM device having a first select transistor and a fir... | 04/01/2008 |
| 7348627 | Nonvolatile semiconductor memory device having element isolating region of trench type Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, an element isolating region comprising an elemen... | 03/25/2008 |
| 7341913 | Method of manufacturing non-volatile memory The invention is directed to a method for manufacturing a non-volatile memory. The method comprises steps of forming a mask layer on a substrate. An isolation structure is formed in the mask layer and the substrate, wherein the top surface of the isolation structure... | 03/11/2008 |
| 7339226 | Dual-level stacked flash memory cell with a MOSFET storage transistor The present invention is a dual-level flash memory cell design that stores 3 or more bits of information per transistor. The dual-level memory cell stores two lower bits in a first level and stores an upper bit in a second level. The lower bits are programmed, erase... | 03/04/2008 |
| 7339230 | Structure and method for making high density mosfet circuits with different height contact lines Embodiments herein present a structure, method, etc. for making high density MOSFET circuits with different height contact lines. The MOSFET circuits include a contact line, a first gate layer situated proximate the contact line, and at least one subsequent gate lay... | 03/04/2008 |
| 7339232 | Semiconductor device having multi-bit nonvolatile memory cell and methods of fabricating the same A semiconductor device having a multi-bit nonvolatile memory cell is provided. The semiconductor device comprises a multi-bit nonvolatile memory unit cell sharing a source and a drain region and having a plurality of transistors. The plurality of transistors each co... | 03/04/2008 |
| 7329577 | Method of manufacturing nonvolatile semiconductor storage device In a method of manufacturing a nonvolatile semiconductor storage device, an element isolation region is formed in a semiconductor substrate, a tunnel oxide film and a polysilicon layer are successively formed on the semiconductor substrate, and nitrogen ions are the... | 02/12/2008 |
| 7323743 | Floating gate A floating gate and fabrication method thereof. A semiconductor substrate is provided, on which an oxide layer, a first conducting layer, and a patterned hard mask layer having an opening are sequentially formed. A spacer is formed on the sidewall of the opening. A ... | 01/29/2008 |
