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| Number | Title | Issue Date |
| 8183621 | Non-volatile memory cell having a heating element and a substrate-based control gate The number of times that a non-volatile memory (NVM) can be programmed and erased is substantially increased by utilizing a localized heating element that anneals the oxide that is damaged by tunneling charge carriers when the NVM is programmed and erased. The progr... | 05/22/2012 |
| 8084807 | Nonvolatile semiconductor memory device and method for manufacturing same A multilayer body is formed by alternately stacking electrode films serving as control gates and dielectric films in a direction orthogonal to an upper surface of a silicon substrate. Trenches extending in the word line direction are formed in the multilayer body an... | 12/27/2011 |
| 8017991 | Non-volatile memory device and methods of operating and fabricating the same Example embodiments provide a non-volatile memory device with increased integration and methods of operating and fabricating the same. A non-volatile memory device may include a plurality of first storage node films and a plurality of first control gate electrodes o... | 09/13/2011 |
| 8004033 | High-density nonvolatile memory Nonvolatile memory cells and methods of forming the same are provided, the methods including forming a first conductor at a first height above a substrate; forming a first pillar-shaped semiconductor element above the first conductor, wherein the first pillar-shaped... | 08/23/2011 |
| 7989875 | BiCMOS integration of multiple-times-programmable non-volatile memories A BiCMOS substrate includes a bipolar area having a buried carrier layer, and a deep trench isolation (DTI) trench extending into the buried carrier layer to form a surface well implant above a buried well implant within the DTI trench, the buried well implant being... | 08/02/2011 |
| 7948024 | Multi-layered, vertically stacked non-volatile memory device and method of fabrication A nonvolatile memory device is provided that includes; a first semiconductor layer extending in a first direction, a second semiconductor layer extending in parallel with and separated from the first semiconductor layer, an isolation layer between the first semicond... | 05/24/2011 |
| 7808033 | Shield plate electrode for semiconductor device A semiconductor device of this invention is a single-layer gate nonvolatile semiconductor memory in which a floating gate having a predetermined shape is formed on a semiconductor substrate. This floating gate opposes a diffusion layer serving as a control gate via ... | 10/05/2010 |
| 7772638 | Non-volatile memory device Provided is a non-volatile memory device that can repetitively perform data write and erase operations in an embedded semiconductor device. In the non-volatile memory device, a device isolation region isolates a first active region and a second active region formed ... | 08/10/2010 |
| 7671401 | Non-volatile memory in CMOS logic process A method, apparatus, and system in which an embedded memory fabricated in accordance with a conventional logic process includes one or more electrically-alterable non-volatile memory cells, each having a programming transistor, a read transistor and a control capaci... | 03/02/2010 |
| 7663180 | Semiconductor device A semiconductor device including: a well layer that is formed on a semiconductor substrate; a first impurity diffusion layer that is formed on the well layer; a floating gate that is formed on the well layer in one region isolated from the first impurity diffusion l... | 02/16/2010 |
| 7652323 | Semiconductor device having step gates and method of manufacturing the same A semiconductor device having step gates includes a semiconductor substrate including first regions having relatively low steps at both ends of an active region defined by trench isolation films and a second region having a relatively high step at a central part of ... | 01/26/2010 |
| 7633115 | Electrically erasable programmable read only memory (EEPROM) cell Semiconductor structures are adapted to form an electrically erasable programmable read only memory (EEPROM) cell having a long retention life, and/or a reduced programming voltage, and/or a reduced semiconductor real estate, and/or a reduced number of semiconductor... | 12/15/2009 |
| 7626225 | Semiconductor device including nonvolatile memory having a floating gate electrode A semiconductor device including a nonvolatile memory element, the nonvolatile memory element, including: a first region, a second region formed adjacent to the first region, and a third region formed adjacent to the second region;... | 12/01/2009 |
| 7602007 | Semiconductor device having controllable transistor threshold voltage A semiconductor device of this invention is a single-layer gate nonvolatile semiconductor memory in which a floating gate having a predetermined shape is formed on a semiconductor substrate. This floating gate opposes a diffusion layer serving as a control gate via ... | 10/13/2009 |
| 7557405 | High-density nonvolatile memory An improved nonvolatile memory cell made by a method for fabricating a three dimensional monolithic memory with increased density. The memory cell includes at least a part of a first conductor, a semiconductor element, and at least a part of a second conductor. The ... | 07/07/2009 |
| 7508027 | Single-poly EPROM device and method of manufacturing The invention relates to a single-poly EPROM comprising a source, a drain, a control gate, a floating gate and an additional gate. The control gate is positioned laterally of a channel between the source and the drain. The floating gate is positioned above the chann... | 03/24/2009 |
| 7508028 | Non-volatile memory A non-volatile memory is provided, including a control gate, a floating gate, a gate oxide layer, a source region, a drain region, a first dielectric layer, a second dielectric layer, and an erase gate. The control gate is disposed in a substrate. The floating gate ... | 03/24/2009 |
| 7442988 | Semiconductor devices and methods of fabricating the same Disclosed is a semiconductor device and method of fabricating the same. The device is disposed on a substrate, including a fin constructed with first and second sidewalls, a first gate line formed in the pattern of spacer on the first sidewall of the fin, and a seco... | 10/28/2008 |
| 7423903 | Single-gate non-volatile memory and operation method thereof A single-gate non-volatile memory and an operation method thereof, wherein a transistor and a capacitor structure are embedded in a semiconductor substrate; the transistor comprises: a first electrically-conductive gate, a first dielectric layer, and multiple ion-do... | 09/09/2008 |
| RE40486 | Self-aligned non-volatile memory cell Disclosed is a self-aligned non-volatile memory cell including a small sidewall spacer electrically coupled and being located next to a main floating gate region. Both the small sidewall spacer and the main floating gate region are formed on a substrate and both for... | 09/09/2008 |
| 7416944 | Flash EEPROM device and method for fabricating the same In a flash EEPROM device, and method for fabricating the same, no bit line contact is made, thereby minimizing a design rule between a contact and a gate. Thus, cell size may be reduced. The flash EEPROM device includes a semiconductor substrate having an active are... | 08/26/2008 |
| 7408221 | Electrically erasable programmable read-only memory cell and memory device and manufacturing method thereof A manufacturing method and a device of an EEPROM cell are provided. The method includes the following steps. First, a tunnel layer and an inter-gate dielectric layer are formed over a surface of a substrate respectively, and a doped region is formed in the substrate... | 08/05/2008 |
| 7408220 | Non-volatile memory and fabricating method thereof A method of fabricating a non-volatile memory is provided. A plurality of columns of isolation structures are formed on a substrate. A plurality of rows of stacked gate structures crossing over the isolation structures are formed on the substrate. A plurality of dop... | 08/05/2008 |
| 7405442 | Electrically erasable programmable read-only memory cell and memory device A manufacturing method and a device of an EEPROM cell are provided. The method includes the following steps. First, a tunnel layer and an inter-gate dielectric layer are formed over a surface of a substrate respectively, and a doped region is formed in the substrate... | 07/29/2008 |
| 7391078 | Non-volatile memory and manufacturing and operating method thereof A non-volatile memory is provided. A substrate having a plurality of trenches and a plurality of select gates is provided. The trenches are arranged in parallel and extend in a first direction. Each of the select gates is disposed on the substrate between two adjace... | 06/24/2008 |
| 7385244 | Flash memory devices with box shaped polygate structures A method for forming an improved etching hardmask oxide layer in a polysilicon etching process including providing a planarized semiconductor wafer process surface including adjacent first exposed polysilicon portions and exposed oxide portions; selectively etching ... | 06/10/2008 |
| 7382015 | Semiconductor device including an element isolation portion having a recess A non-volatile semiconductor memory device, which is intended to prevent data destruction by movements of electric charges between floating gates and thereby improve the reliability, includes element isolation/insulation films buried into a silicon substrate to isol... | 06/03/2008 |
| 7375393 | Non-volatile memory (NVM) retention improvement utilizing protective electrical shield An electrical shield is provided in a non-volatile memory (NVM) cell structure to protect the cell's floating gate from any influence resulting from charge redistribution in the vicinity of the floating gate during a programming operation. The shield may be created ... | 05/20/2008 |
| 7372098 | Low power flash memory devices A buried bipolar junction is provided in a floating gate transistor flash memory device. During a write operation electrons are injected into a surface depletion region of the memory cell transistors. These electrons are accelerated in a vertical electric field and ... | 05/13/2008 |
| 7372734 | Methods of operating electrically alterable non-volatile memory cell A nonvolatile memory cell is provided. The memory cell includes a storage transistor and an injector in a well of an n-type conductivity. The well is formed in a semiconductor substrate of a p-type conductivity. The storage transistor comprises a source, a drain, a ... | 05/13/2008 |
| 7365383 | Method of forming an EPROM cell and structure therefor An EPROM cell includes a control gate and a control transistor. A portion of the control transistor is formed as a portion of the control gate. ... | 04/29/2008 |
| 7355237 | Shield plate for limiting cross coupling between floating gates A memory system is disclosed that includes a set of non-volatile storage elements. Each of said non-volatile storage elements includes source/drain regions at opposite sides of a channel in a substrate and a floating gate stack above the channel. The memory system a... | 04/08/2008 |
| 7348621 | Non-volatile memory cells A non-volatile memory cell and method of fabrication are provided. The non-volatile memory cell includes a substrate of a first conductivity type, a first dopant region of a second conductivity type in the substrate, a second dopant region of the first conductivity ... | 03/25/2008 |
| 7342276 | Method and apparatus utilizing monocrystalline insulator A semiconductor device, including: a semiconductor material; a conductive element; and a substantially monocrystalline insulator disposed between the semiconductor material and the conductive eleme... | 03/11/2008 |
| 7339230 | Structure and method for making high density mosfet circuits with different height contact lines Embodiments herein present a structure, method, etc. for making high density MOSFET circuits with different height contact lines. The MOSFET circuits include a contact line, a first gate layer situated proximate the contact line, and at least one subsequent gate lay... | 03/04/2008 |
| 7339835 | Non-volatile memory structure and erase method with floating gate voltage control Feedback between the floating gate voltage and a high erase voltage is utilized in the erase operation of a non-volatile memory (NVM) cell. Erasing stops when the floating gate voltage reaches the threshold voltage of the controlling transistor, making the variabili... | 03/04/2008 |
| 7339229 | Nonvolatile memory solution using single-poly pFlash technology A single-poly two-transistor PMOS memory cell for multiple-time programming applications includes a PMOS floating gate transistor sharing a drain/source P+ diffusion region with a PMOS select gate transistor all formed within a first n-well. A control plate for the ... | 03/04/2008 |
| 7336535 | Semiconductor integrated circuit device A nonvolatile storage element of a single-layer gate type structure is arranged so that a floating gate is formed of a conductive layer which partly overlaps with a control gate, formed of a diffused layer, and is provided with a barrier layer covering a part of or ... | 02/26/2008 |
| 7332789 | Isolation trenches for memory devices Methods and apparatus are provided. A first dielectric plug is formed in a portion of a trench that extends into a substrate of a memory device so that an upper surface of the first dielectric plug is recessed below an upper surface of the substrate. The first diele... | 02/19/2008 |
| 7332769 | Non-volatile memory arrangement having nanocrystals The amount of current flowing in the bitline during reading of a memory cell which is in the conductive state, hereinafter called the memory cell current, can be amplified manifold by changing the above mentioned select transistors to a novel device which is describ... | 02/19/2008 |
