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| Number | Title | Issue Date |
| 8183613 | Bipolar transistor for a memory array A memory device includes an insulation layer, an active pattern, a gate insulation layer and a gate electrode. The insulation layer is formed on a substrate. The active pattern is formed on the insulation layer, and includes two protrusions and a recess between the ... | 05/22/2012 |
| 8164133 | Vertical transistor and method of enabling a vertical transistor to generate an alternating current output A vertical transistor includes a gate isolating layer flanking a stack of a source layer, a resilient active unit and a drain layer, and a gate layer formed on the gate isolating layer. The active unit includes an active layer formed between first and second barrier... | 04/24/2012 |
| 8138538 | Interconnect structure for semiconductor devices One embodiment relates to an integrated circuit formed on a semiconductor body having interconnect between source/drain regions of a first and second transistor. The interconnect includes a metal body arranged underneath the surface of the semiconductor body. A cont... | 03/20/2012 |
| 8120085 | Semiconductor device and method for manufacturing the same A semiconductor device includes: a channel region extending substantially perpendicular to a main surface of a semiconductor substrate; a first diffusion layer provided on a bottom of the channel region; a second diffusion layer provided on a top of the channel regi... | 02/21/2012 |
| 8053823 | Simplified buried plate structure and process for semiconductor-on-insulator chip A structure is provided herein which includes an array of trench capacitors having at least portions disposed below a buried oxide layer of an SOI substrate. Each trench capacitor shares a common unitary buried capacitor plate which includes at least a portion of a ... | 11/08/2011 |
| 8022456 | Checkerboarded high-voltage vertical transistor layout In one embodiment, a transistor fabricated on a semiconductor die includes a first section of transistor segments disposed in a first area of the semiconductor die, and a second section of transistor segments disposed in a second area of the semiconductor die adjace... | 09/20/2011 |
| 7994559 | Recessed-gate transistor device having a dielectric layer with multi thicknesses and method of making the same A recessed-gate transistor device includes a gate electrode embedded in a gate trench formed in a semiconductor substrate, wherein the gate trench includes a vertical sidewall and a U-shaped bottom. A source region is provided at one side of the gate trench within t... | 08/09/2011 |
| 7989866 | DRAM layout with vertical FETS and method of formation DRAM cell arrays having a cell area of about 4 F2 comprise an array of vertical transistors with buried bit lines and vertical double gate electrodes. The buried bit lines comprise a silicide material and are provided below a surface of the substrate. The... | 08/02/2011 |
| 7968928 | DRAM layout with vertical FETs and method of formation DRAM cell arrays having a cell area of less than about 4 F2 comprise an array of vertical transistors with buried bit lines and vertical double gate electrodes. The buried bit lines comprise a silicide material and are provided below a surface of the subs... | 06/28/2011 |
| 7936000 | Vertical wrap-around-gate field-effect-transistor for high density, low voltage logic and memory array A vertical transistor having a wrap-around-gate and a method of fabricating such a transistor. The wrap-around-gate (WAG) vertical transistors are fabricated by a process in which source, drain and channel regions of the transistor are automatically defined and alig... | 05/03/2011 |
| 7928490 | Vertical transistor and vertical transistor array A vertical transistor including a substrate, a gate, a base line and a gate dielectric layer is provided. The substrate includes a pillar protruding out of a surface of the substrate. The pillar includes a first doped region, a channel region and a second doped regi... | 04/19/2011 |
| 7898014 | Semiconductor device structures with self-aligned doped regions and methods for forming such semiconductor device structures Semiconductor device structures with self-aligned doped regions and methods for forming such semiconductor device structures. The semiconductor structure comprises first and second doped regions of a first conductivity type defined in the semiconductor material of a... | 03/01/2011 |
| 7859037 | Checkerboarded high-voltage vertical transistor layout In one embodiment, a transistor fabricated on a semiconductor die is arranged into sections of elongated transistor segments. The sections are arranged in rows and columns substantially across the semiconductor die. Adjacent sections in a row or a column are oriente... | 12/28/2010 |
| 7851842 | Vertical channel transistor in semiconductor device and method of fabricating the same A method of fabricating a vertical channel transistor for a semiconductor device includes forming, on a substrate, a plurality of active pillars each having a gate electrode formed on and surrounding a lower portion thereof; forming a first insulation layer over the... | 12/14/2010 |
| 7847329 | Vertical MOSFET transistor, in particular operating as a selector in nonvolatile memory devices A vertical MOSFET transistor is formed in a body of semiconductor material having a surface. The transistor includes a buried conductive region of a first conductivity type; a channel region of a second conductivity type, arranged on top of the buried conductive reg... | 12/07/2010 |
| 7816720 | Trench MOSFET structure having improved avalanche capability using three masks process A trench MOSFET structure having improved avalanche capability is disclosed, wherein the source region is formed by performing source Ion Implantation through contact open region of a thick contact interlayer, and further diffused to optimize a trade-off between Rds... | 10/19/2010 |
| 7808029 | Mask structure for manufacture of trench type semiconductor device A mask structure and process for forming trenches in a silicon carbide or other wafer, and for implanting impurities into the walls of the trenches using the same mask where the mask includes a thin aluminum layer and a patterned hard photoresist mask. A thin LTO ox... | 10/05/2010 |
| 7800152 | Methods for manufacturing a finfet using a conventional wafer and apparatus manufactured therefrom A method is provided for producing a fin structure on a semiconductor substrate using a thin SiGe layer to produce a void between a silicon substrate and a silicon fin portion. A fin structure produced by such a method is also provided. ... | 09/21/2010 |
| 7795661 | Vertical SOI transistor memory cell The present invention relates to a semiconductor device that contains at least one trench capacitor and at least one vertical transistor, and methods for forming such a semiconductor device. Specifically, the trench capacitor is located in a semiconductor substrate ... | 09/14/2010 |
| 7781817 | Structures, fabrication methods, and design structures for multiple bit flash memory cells A semiconductor structure, a fabrication method, and a design structure of the same. The semiconductor structure includes (i) a semiconductor substrate which includes a top substrate surface perpendicular to the top substrate surface, (ii) a control gate electrode r... | 08/24/2010 |
| 7772633 | DRAM cells with vertical transistors The invention includes a semiconductor structure having U-shaped transistors formed by etching a semiconductor substrate. In an embodiment, the source/drain regions of the transistors are provided at the tops of pairs of pillars defined by crossing trenches in the s... | 08/10/2010 |
| 7750389 | NROM memory cell, memory array, related devices and methods An array of memory cells configured to store at least one bit per one F2 includes substantially vertical structures providing an electronic memory function spaced apart a distance equal to one half of a minimum pitch of the array. The structures providing... | 07/06/2010 |
| 7732848 | Power semiconductor device with improved heat dissipation A semiconductor device is disclosed that improves heat dissipation by providing blind contact elements on a dielectric layer. Embodiments are disclosed which include a substrate having at least one electrode contact area accessible at a surface of the substrate and ... | 06/08/2010 |
| 7732849 | Dynamic random access memory A dynamic random access memory (DRAM) is provided. The DRAM comprises a substrate, a vertical transistor, a deep trench capacitor and a buried strap. The substrate has a trench and a deep trench located on one side of the trench thereon. The vertical transistor is d... | 06/08/2010 |
| 7723768 | Asymmetric recessed gate MOSFET and method for manufacturing the same Disclosed are an asymmetric recessed gate MOSFET, and a method for manufacturing the same. The asymmetric recessed gate MOSFET comprises: recess regions formed at a predetermined depth in a semiconductor; recessed gate electrodes formed at a predetermined height on ... | 05/25/2010 |
| 7679121 | Ultra scalable high speed heterojunction vertical n-channel MISFETs and methods thereof A method for forming and the structure of a strained vertical channel of a field effect transistor, a field effect transistor and CMOS circuitry is described incorporating a drain, body and source region on a sidewall of a vertical single crystal semiconductor struc... | 03/16/2010 |
| 7655968 | Semiconductor devices A method for forming double-sided capacitors for a semiconductor device includes forming a dielectric structure which supports capacitor bottom plates during wafer processing. The structure is particularly useful for supporting the bottom plates during removal of a ... | 02/02/2010 |
| 7642588 | Memory cells with planar FETs and vertical FETs with a region only in upper region of a trench and methods of making and using same In a first aspect, a first apparatus is provided. The first apparatus is a memory cell of a substrate that includes (1) a PFET with an orientation approximately planar to a surface of the substrate; and (2) an NFET coupled to the approximately planar PFET. An orient... | 01/05/2010 |
| 7642589 | Fin field effect transistors having capping insulation layers A field effect transistor includes a vertical fin-shaped semiconductor active region having an upper surface and a pair of opposing sidewalls on a substrate, and an insulated gate electrode on the upper surface and opposing sidewalls of the fin-shaped active region.... | 01/05/2010 |
| 7626223 | Memory structure for reduced floating body effect Methods of reducing the floating body effect in vertical transistors are disclosed. The floating body effect occurs when an active region in a pillar is cut off from the substrate by a depletion region and the accompanying electrostatic potential created. In a prefe... | 12/01/2009 |
| 7615817 | Methods of manufacturing semiconductor devices and semiconductor devices manufactured using such a method A method of manufacturing a semiconductor device includes forming a pillar-shaped active region by etching a portion of a semiconductor substrate, forming a blocking film selectively exposing a sidewall of a lower portion of the pillar-shaped active region, and form... | 11/10/2009 |
| 7595524 | Power device with trenches having wider upper portion than lower portion A field effect transistor includes a plurality of trenches extending into a silicon layer. Each trench has upper sidewalls that fan out. Contact openings extend into the silicon layer between adjacent trenches such that each trench and an adjacent contact opening fo... | 09/29/2009 |
| 7595523 | Gate pullback at ends of high-voltage vertical transistor structure In one embodiment, a transistor includes a pillar of semiconductor material arranged in a racetrack-shaped layout having a substantially linear section that extends in a first lateral direction and rounded sections at each end of the substantially linear section. Fi... | 09/29/2009 |
| 7564087 | Merged MOS-bipolar capacitor memory cell A high density vertical merged MOS-bipolar-capacitor gain cell is realized for DRAM operation. The gain cell includes a vertical MOS transistor having a source region, a drain region, and a floating body region therebetween. The gain cell includes a vertical bi-pola... | 07/21/2009 |
| 7564088 | High-density single transistor vertical memory gain cell A memory cell which is formed on a substrate of a first conductivity type. A pillar of the first conductivity type extends vertically upward from the substrate. A source region of a second conductivity type is formed in the substrate extending adjacent to and away f... | 07/21/2009 |
| 7521747 | Vertical transistor and a semiconductor integrated circuit apparatus having the same AMOS transistor comprises: a first conduction type region; a second conduction type drain region formed on the outermost layer portion of the first conduction type region; a second conduction type source region formed on the outermost layer portion of the first cond... | 04/21/2009 |
| 7489003 | Semiconductor device having a channel extending vertically In a semiconductor device, the semiconductor device includes a conductive structure, first insulating layers and first conductive layer patterns. The conductive structure includes a first portion, second portions and third portions. The second portions extend in a f... | 02/10/2009 |
| 7485910 | Simplified vertical array device DRAM/eDRAM integration: method and structure The present invention provides a semiconductor structure that includes an active wordline located above a semiconductor memory device and a passive wordline located adjacent to said active wordline and above an active area of a substrate. In accordance with the pres... | 02/03/2009 |
| 7482650 | Method of manufacturing a semiconductor integrated circuit device having a columnar laminate For improving the filling properties between vertical MISFETs constituting a SRAM memory cell, the vertical MISFETs are formed over horizontal drive MISFETs and transfer MISFETs, and they are disposed with a narrow pitch in the Y direction and a wide pitch in the X ... | 01/27/2009 |
| 7482649 | Multi-bit nonvolatile memory devices Multi-bit nonvolatile memory devices and related methods of manufacturing the same are described. In some multi-bit nonvolatile memory devices, a semiconductor substrate has a recessed region defined therein. An insulating layer, which can include an ONO layer, is c... | 01/27/2009 |
