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| Number | Title | Issue Date |
| 8035148 | Micromachined transducer integrated with a charge pump An integrated circuit includes a micromachined transducer and a charge pump. More particularly, on one silicon substrate, a control circuit delivers high voltage from the charge pump to operate the transducer. An electronic apparatus, such as a cell phone or automat... | 10/11/2011 |
| 7968925 | Power semiconductor module for inverter circuit system A double-face-cooled semiconductor module with an upper arm and a lower arm of an inverter circuit includes first and second heat dissipation members, each having a heat dissipation surface on one side and a conducting member formed on another side through an insula... | 06/28/2011 |
| 7956397 | Semiconductor device, charge pumping circuit, and semiconductor memory circuit A semiconductor device comprising: a first well region which is formed at a surface portion of a semiconductor substrate and to which a first voltage is applied; a gate insulating film which is formed on the first ... | 06/07/2011 |
| 7829928 | Semiconductor structure of a high side driver and method for manufacturing the same A semiconductor structure of a high side driver and method for manufacturing the same is disclosed. The semiconductor of a high side driver includes an ion-doped junction and an isolation layer formed on the ion-doped junction. The ion-doped junction has a number of... | 11/09/2010 |
| 7825448 | U-shaped SONOS memory having an elevated source and drain A semiconductor device and a method for manufacturing thereof are provided. The semiconductor device includes two epitaxial semiconductor layers formed on a semiconductor substrate, bit lines formed on upper portions of the two epitaxial semiconductor layers, and a ... | 11/02/2010 |
| 7705385 | Selective deposition of germanium spacers on nitride A method of selectively forming a germanium structure within semiconductor manufacturing processes removes the native oxide from a nitride surface in a chemical oxide removal (COR) process and then exposes the heated nitride and oxide surface to a heated germanium c... | 04/27/2010 |
| 7667254 | Semiconductor integrated circuit device Wiring is routed to assure insulation between wiring traces in a semiconductor integrated circuit device. The device includes a first wiring trace to which a prescribed voltage is supplied; a second wiring trace that takes on a voltage that exceeds the prescribed vo... | 02/23/2010 |
| 7626222 | Capacitor arrangement in a semiconductor component and driving apparatus A semiconductor device includes a first capacitor node, a second capacitor node, a first capacitor electrode, a second capacitor electrode, a first switch and a second switch. The first switch is coupled between the first capacitor electrode and the first and second... | 12/01/2009 |
| 7436015 | Driver for driving a load using a charge pump circuit A charge pump circuit includes MOSFETs and MOS capacitors formed on the same substrate. Each of the MOS capacitors has a multiplicity of first electrodes formed in one region of the substrate, insulating layers formed on/above respective substrate regions between ne... | 10/14/2008 |
| 7428169 | Nonvolatile semiconductor memory device and voltage generating circuit for the same A nonvolatile semiconductor memory device includes a memory cell array of a plurality of memory cells; and a voltage generating circuit for generating a programming voltage to be applied to the memory cells. The voltage generating circuit includes a first voltage ge... | 09/23/2008 |
| 7425725 | Temperature sensor for a liquid crystal display panel A sensor is provided, which includes a substrate, an insulating layer formed on the substrate, a semiconductor formed on the insulating layer, an ohmic contact formed on the semiconductor, a sensor input electrode and a sensor output electrode formed on the ohmic co... | 09/16/2008 |
| 7382014 | Semiconductor device with capacitor suppressing leak current A semiconductor device with a capacitor includes a lower electrode, a dielectric and an upper electrode on the dielectric layer. The dielectric layer including more than one polycrystalline tantalum oxide layer and more than one separation layer, wherein the polycry... | 06/03/2008 |
| 7378739 | Capacitor and light emitting display using the same A capacitor including a polysilicon layer doped with impurities to be conductive, a first dielectric layer formed on the polysilicon layer, a first conductive layer formed on the first dielectric layer, a second dielectric layer formed on the first conductive layer,... | 05/27/2008 |
| 7375376 | Semiconductor display device and method of manufacturing the same A semiconductor display device with an interlayer insulating film in which surface levelness is ensured with a limited film formation time, heat treatment for removing moisture does not take long, and moisture in the interlayer insulating film is prevented from esca... | 05/20/2008 |
| 7361957 | Device for electrostatic discharge protection and method of manufacturing the same The present invention relates to a device for electrostatic discharge protection (ESD). According to an embodiment of the present invention, a device for electrostatic discharge protection includes a semiconductor substrate, a plurality of field oxide films formed i... | 04/22/2008 |
| 7358573 | Triple-well CMOS devices with increased latch-up immunity and methods of fabricating same A triple-well CMOS structure having reduced latch-up susceptibility and a method of fabricating the structure. The method includes forming a buried P-type doped layer having low resistance under the P-wells and N-wells in which CMOS transistors are formed and formin... | 04/15/2008 |
| 7348251 | Modulated trigger device An integrated circuit structure, a trigger device and a method of electrostatic discharge protection, the integrated circuit structure including: a substrate having a top surface defining a horizontal direction, the substrate of a first dopant type; a first horizont... | 03/25/2008 |
| 7342438 | N-channel negative charge pump Described herein is a negative charge pump architecture that utilizes a triple-well, no body effect NMOS circuitry. The negative charge pump utilizes triple-well N channel high mobility transistor devices with the deep N wells grounded. The parasitic bipolar transis... | 03/11/2008 |
| 7342276 | Method and apparatus utilizing monocrystalline insulator A semiconductor device, including: a semiconductor material; a conductive element; and a substantially monocrystalline insulator disposed between the semiconductor material and the conductive eleme... | 03/11/2008 |
| 7342291 | Standby current reduction over a process window with a trimmable well bias An integrated circuit device including a plurality of MOSFETs of similar type and geometry is formed on a substrate with an ohmic contact, and an adjustable voltage source on the die utilizing clearable fuses is coupled between the ohmic contact and the sources of t... | 03/11/2008 |
| 7332763 | Selective coupling of voltage feeds for body bias voltage in an integrated circuit device An integrated circuit device having a body bias voltage mechanism. The integrated circuit comprises a resistive structure disposed therein for selectively coupling either an external body bias voltage or a power supply voltage to biasing wells. A first pad for coupl... | 02/19/2008 |
| 7326990 | Semiconductor device and method for fabricating the same A semiconductor device includes a first hydrogen barrier film, a capacitor device formed on the first hydrogen barrier film, and a second hydrogen barrier film formed to cover the capacitor device. The first and second hydrogen barrier films each contain at least on... | 02/05/2008 |
| 7323708 | Phase change memory devices having phase change area in porous dielectric layer A phase change memory device includes a lower electrode and a porous dielectric layer having fine pores on the lower electrode. A phase change layer is provided in the fine pores of the porous dielectric layer. An upper electrode is provided on the phase change laye... | 01/29/2008 |
| 7323753 | MOS transistor circuit and voltage-boosting booster circuit To an output of an NMOS having one end connected to a power source, a capacitor and a PMOS are connected. A capacitor is connected to the output of the PMOS. The NMOS and the PMOS are turned on alternately. A pulse is applied to other end of the capacitor which is c... | 01/29/2008 |
| 7319254 | Semiconductor memory device having resistor and method of fabricating the same A semiconductor device having resistors in a peripheral area and fabrication method thereof are provided. A mold layer is formed on a semiconductor substrate. The mold layer is patterned to form first molding holes and a second molding hole in the mold layer. A stor... | 01/15/2008 |
| 7319357 | System for controlling switch transistor performance The present invention provides a system for controlling performance of a switch transistor (106)—one that is implemented within a circuitry segment (100) to shut off a circuitry component (116) when that component is not in use. The switch tra... | 01/15/2008 |
| 7301388 | Charge pump with ensured pumping capability An n-stage charge pump contains n primary capacitive elements (CC1-CCn or CD1-CDn), n+1 charge-transfer cells (601-60n+1, 1101-110n+1, 1201-120n+1, or 130 | 11/27/2007 |
| 7298000 | Conductive container structures having a dielectric cap Container structures for use in integrated circuits and methods of their manufacture. The container structures have a dielectric cap on the top of a conductive container to reduce the risk of container-to-container shorting by insulating against bridging of conducti... | 11/20/2007 |
| 7295198 | Voltage booster circuit, power supply circuit, and liquid crystal driver A charge-pump circuit includes: MOS transistors connected in series and having one end to which a system ground power supply voltage is supplied; and a discharge transistor. The discharge transistor has one end connected to a node which is connected to the MOS trans... | 11/13/2007 |
| 7292089 | Charge pump circuit with no output voltage loss The present invention is for preventing a charge pump from an unnecessary output voltage loss generated by a threshold voltage of a metal-oxide silicon (MOS) transistor. An apparatus for amplifying an inputted voltage includes an amplifying block including at least ... | 11/06/2007 |
| 7288806 | DRAM arrays The invention includes memory arrays, and methods which can be utilized for forming memory arrays. A patterned etch stop can be used during memory array fabrication, with the etch stop covering storage node contact locations while leaving openings to bitline contact... | 10/30/2007 |
| 7279745 | Semiconductor device In a semiconductor device of the present invention, an N-type epitaxial layer 2 is deposited on a P-type substrate 1. In the epitaxial layer 2, a P-type diffusion layer 5 to be used as a back gate region is formed. An N-type diffusion lay... | 10/09/2007 |
| 7279699 | Integrated circuit comprising a waveguide having an energy band engineered superlattice An integrated circuit may include at least one active optical device and a waveguide coupled thereto. The waveguide may include a superlattice including a plurality of stacked groups of layers. Each group of layers of the superlattice may include a plurality of stac... | 10/09/2007 |
| 7276419 | Semiconductor device and method for forming the same A semiconductor device may include first, second, and third semiconductor layers. The first and third layers may have a first dopant type, and the second layer may have a second dopant type. A first region within the third semiconductor layer may have the second dop... | 10/02/2007 |
| 7276751 | Trench metal-insulator-metal (MIM) capacitors integrated with middle-of-line metal contacts, and method of fabricating same The present invention relates to a semiconductor device that contains at least one trench metal-oxide-metal (MIM) capacitor and at least one other logic circuitry component, preferably at least one field effect transistor (FET). The trench MIM capacitor is located i... | 10/02/2007 |
| 7268400 | Triple-well CMOS devices with increased latch-up immunity and methods of fabricating same A triple-well CMOS structure having reduced latch-up susceptibility and a method of fabricating the structure. The method includes forming a buried P-type doped layer having low resistance under the P-wells and N-wells in which CMOS transistors are formed and formin... | 09/11/2007 |
| 7262092 | High-voltage CMOS-compatible capacitors A high-voltage stacked capacitor includes a first capacitor and a second capacitor. Each capacitor includes a first plate having a first semiconductive body and a second plate having a floating electrode. The first and second semiconductive bodies are electrically i... | 08/28/2007 |
| 7256438 | MOS capacitor with reduced parasitic capacitance A capacitor including a first active layer capacitively coupled to a second active layer, the second active layer being capacitively coupled to a third layer, the third layer being capacitively coupled to a fourth layer, wherein an anode of the capacitor is connecte... | 08/14/2007 |
| 7253519 | Chip packaging structure having redistribution layer with recess A chip structure comprising a chip, a redistribution layer, a second passivation layer and at least a bump is provided. The chip has a first passivation layer and at least a bonding pad. The first passivation layer exposes the bonding pad and has at least a recess. ... | 08/07/2007 |
| 7244982 | Semiconductor device using a conductive film and method of manufacturing the same A semiconductor device has a capacitive element including a first conductive film formed on the bottom and wall surfaces of an opening formed in an insulating film on a substrate, a dielectric film formed on the first conductive film, and a second conductive film fo... | 07/17/2007 |
