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| Number | Title | Issue Date |
| 8110861 | MIM capacitor high-k dielectric for increased capacitance density According to one embodiment of the invention, a method for fabricating a MIM capacitor in a semiconductor die includes a step of depositing a first interconnect metal layer. The method further includes depositing a high-k dielectric layer comprising AlNX ... | 02/07/2012 |
| 8106435 | Method of forming a semiconductor device having an etch stop layer and related device In one embodiment, a lower interlayer dielectric layer, and first and second landing pads penetrating the lower interlayer dielectric layer are formed on a substrate. Interconnection patterns covering the second landing pads are formed on the lower interlayer dielec... | 01/31/2012 |
| 8097910 | Vertical transistors The invention includes a semiconductor structure having U-shaped transistors formed by etching a semiconductor substrate. In an embodiment, the source/drain regions of the transistors are provided at the tops of pairs of pillars defined by crossing trenches in the s... | 01/17/2012 |
| 8093637 | MIM capacitor and associated production method An MIM capacitor includes a first capacitor electrode, which is formed in the surface of a first intermediate dielectric, a second intermediate dielectric, which is formed on the first intermediate dielectric and has an opening that exposes the first capacitor elect... | 01/10/2012 |
| 8093638 | Systems with a gate dielectric having multiple lanthanide oxide layers Electronic systems and methods of forming the electronic systems include a gate dielectric having multiple lanthanide oxide layers. Such electronic systems may be used in a variety of electronic system applications. A dielectric film having a layer of a lanthanide o... | 01/10/2012 |
| 8093639 | Method for fabricating a semiconductor device An embodiment of the invention provides a method for forming a semiconductor device comprising providing a substrate with a pad layer formed thereon. The pad layer and the substrate are patterned to form a plurality of trenches. A trench top insulating layer is form... | 01/10/2012 |
| 8084801 | Cell structure for a semiconductor memory device and method of fabricating the same In a 6F2 cell structure of a memory device and a method of fabricating the same, the plurality of active regions may have a first area at both end portions and a second area at a central portion. A portion of a bit-line contact pad may be positioned on th... | 12/27/2011 |
| 8084799 | Integrated circuit with memory having a step-like programming characteristic A memory cell includes a first electrode, a second electrode, and phase change material between the first electrode and the second electrode. The phase change material has a step-like programming characteristic. The first electrode, the second electrode, and the pha... | 12/27/2011 |
| 8084800 | Semiconductor device and a method of manufacturing the same In connection with a semiconductor device including a capacitor element there is provided a technique capable of improving the reliability of the capacitor element. A capacitor element is formed in an element isolation region formed over a semiconductor substrate. T... | 12/27/2011 |
| 8084802 | Nonvolatile semiconductor memory A select gate transistor has a select gate electrode composed of a first-level conductive layer and a second-level conductive layer. The first-level conductive layer has contact areas. The second-level conductive layer has its portions removed that are located above... | 12/27/2011 |
| 8058679 | Semiconductor device and semiconductor device manufacturing method A semiconductor device including a semiconductor substrate having a logic formation region where a logic device is formed; a first impurity region formed in an upper surface of the semiconductor substrate in the logic formation region; a second impurity region forme... | 11/15/2011 |
| 8058678 | Semiconductor memory device including a cylinder type storage node and a method of fabricating the same Provided is a semiconductor memory device including cylinder type storage nodes and a method of fabricating the semiconductor memory device. The semiconductor memory device includes: a semiconductor substrate including switching devices; a recessed insulating layer ... | 11/15/2011 |
| 8053822 | Capacitorless DRAM and methods of manufacturing and operating the same Example embodiments provide a capacitorless dynamic random access memory (DRAM), and methods of manufacturing and operating the same. The capacitorless DRAM according to example embodiments may include a semiconductor layer separated from a top surface of a substrat... | 11/08/2011 |
| 8049258 | Disposable pillars for contact formation Sacrificial plugs for forming contacts in integrated circuits, as well as methods of forming connections in integrated circuit arrays are disclosed. Various pattern transfer and etching steps can be used to create densely-packed features and the connections between ... | 11/01/2011 |
| 8049259 | Semiconductor device including memory cell having charge accumulation layer A semiconductor device includes MOS transistors, capacitor elements, a voltage generating circuit, a contact plug, and a memory cell. The MOS transistor and the capacitor element are formed on a first one of the element regions and a second one of the element region... | 11/01/2011 |
| 8044448 | Nonvolatile semiconductor memory device A nonvolatile semiconductor memory device includes: a memory cell array region having memory cells connected in series; a control circuit region disposed below the memory cell array region; and an interconnection portion electrically connecting the control circuit r... | 10/25/2011 |
| 8035147 | Semiconductor device A high-speed and low-voltage DRAM memory cell capable of operating at 1 V or less and an array peripheral circuit are provided. A DRAM cell is comprised of a memory cell transistor and planar capacitor which utilize a FD-SOI MOST structure. Since there is no junctio... | 10/11/2011 |
| 8026542 | Low resistance peripheral local interconnect contacts with selective wet strip of titanium Methods for forming memory devices and integrated circuitry, for example, DRAM circuitry, structures and devices resulting from such methods, and systems that incorporate the devices are provided. ... | 09/27/2011 |
| 8026543 | Semiconductor devices having phase change memory cells, electronic systems employing the same and methods of fabricating the same A phase-change memory device has an oxidation barrier layer to protect against memory cell contamination or oxidation. In one embodiment, a semiconductor memory device includes a molding layer disposed over semiconductor substrate, a phase-changeable material patter... | 09/27/2011 |
| 8022455 | Method of fabricating semiconductor device for reducing parasitic capacitance between bit lines and semiconductor device fabricated thereby In a method of fabricating a semiconductor device capable of reducing parasitic capacitance between bit lines and a semiconductor device fabricated by the method, the semiconductor device includes a semiconductor substrate having buried contact landing pads and dire... | 09/20/2011 |
| 8013375 | Semiconductor memory devices including diagonal bit lines A semiconductor memory device may include a semiconductor substrate having a plurality of active regions wherein each active region has a length in a direction of a first axis and a width in a direction of a second axis. The length may be greater than the width, and... | 09/06/2011 |
| 8013376 | Memory arrays, semiconductor constructions and electronic systems with transistor gates extending partially over SOI and unit cells within active region pedestals Some embodiments include DRAM having transistor gates extending partially over SOI, and methods of forming such DRAM. Unit cells of the DRAM may be within active region pedestals, and in some embodiments the unit cells may comprise capacitors having storage nodes in... | 09/06/2011 |
| 8013373 | Semiconductor device having MOS-transistor formed on semiconductor substrate and method for manufacturing thereof A semiconductor device comprises MOS transistors sequentially arranged in the plane direction of a substrate, wherein a gate electrode and a wiring portion for connecting between the gate electrodes to each other are implanted into a layer that is lower than a surfa... | 09/06/2011 |
| 8013371 | Ultra thin TCS (SiCl) cell nitride for DRAM capacitor with DCS (SiHCl) interface seeding layer A method for forming silicon nitride films on semiconductor devices is provided. In one embodiment of the method, a silicon-comprising substrate is first exposed to a mixture of dichlorosilane (DCS) and a nitrogen-comprising gas to deposit a thin silicon nitride see... | 09/06/2011 |
| 8013372 | Integrated circuit including a stressed dielectric layer with stable stress A method for fabricating an integrated circuit is provided. The method includes providing a substrate having an active region and an opening in the substrate adjacent to the active region. The opening is filled with a dielectric material so as to provide an isolatio... | 09/06/2011 |
| 8013374 | Semiconductor memory devices including offset bit lines A semiconductor memory device may include a substrate having a plurality of active regions wherein each active region has a length in a direction of a first axis and a width in a direction of a second axis. The length may be greater than the width, and the plurality... | 09/06/2011 |
| 8008699 | Semiconductor device with circuit for reduced parasitic inductance Parasitic inductance of the main circuit of a power source unit is reduced. In a non-insulated DC-DC converter having a circuit in which a power MOSFET for high side switch and a power MOSFET for low side switch are connected in series, the power MOSFET for high sid... | 08/30/2011 |
| 8008698 | Semiconductor memory devices having vertical channel transistors and related methods A semiconductor memory device may include a semiconductor substrate with an active region extending in a first direction parallel with respect to a surface of the semiconductor substrate. A pillar may extend from the active region in a direction perpendicular with r... | 08/30/2011 |
| 8004030 | Semiconductor device and method for manufacturing the same Provided is a semiconductor device that includes: a base insulating film 25 formed above a silicon substrate 10; a ferroelectric capacitor Q formed on the base insulating film 25; multiple interlayer insulating films 35, 48, and 62, | 08/23/2011 |
| 7999295 | Stacked thin film transistor, non-volatile memory devices and methods for fabricating the same A manufacturing method for stacked, non-volatile memory devices provides a plurality of bitline layers and wordline layers with charge trapping structures. The bitline layers have a plurality of bitlines formed on an insulating layer, such as silicon on insulator te... | 08/16/2011 |
| 7999294 | Semiconductor device which may prevent electrical failures of contacts A semiconductor device includes a first insulation film having a plurality of openings which exposes predetermined regions of a semiconductor substrate, a plurality of first conductive patterns partially filling the openings and a plurality of second conductive patt... | 08/16/2011 |
| 7994556 | Semiconductor memory device having amorphous contact plug A semiconductor memory device includes: a semiconductor substrate; a field effect transistor formed on the semiconductor substrate; an interlayer dielectric layer formed on the field effect transistor; a contact plug connected to the field effect transistor through ... | 08/09/2011 |
| 7994557 | Non-volatile memory cells employing a transition metal oxide layer as a data storage material layer and methods of manufacturing the same Non-volatile memory cells employing a transition metal oxide layer as a data storage material layer are provided. The non-volatile memory cells include a lower and upper electrodes overlapped with each other. A transition metal oxide layer pattern is provided betwee... | 08/09/2011 |
| 7989863 | Method of forming a semiconductor device having an etch stop layer and related device In one embodiment, a lower interlayer dielectric layer, and first and second landing pads penetrating the lower interlayer dielectric layer are formed on a substrate. Interconnection patterns covering the second landing pads are formed on the lower interlayer dielec... | 08/02/2011 |
| 7985995 | Zr-substituted BaTiOfilms The use of atomic layer deposition (ALD) to form a zirconium substituted layer of barium titanium oxide (BaTiO3), produces a reliable ferroelectric structure for use in a variety of electronic devices such as a dielectric in nonvolatile random access memo... | 07/26/2011 |
| 7985996 | Semiconductor device comprising capacitive elements A technology capable of reducing the fraction defective of a MOS capacitor without the need to perform a screening is provided. A MOS capacitor MOS1 and a MOS capacitor MOS2 are coupled in series between a high potential and a low potential to form a s... | 07/26/2011 |
| 7982253 | Semiconductor device with a dynamic gate-drain capacitance A semiconductor device with a dynamic gate drain capacitance. One embodiment provides a semiconductor device. The device includes a semiconductor substrate, a field effect transistor structure including a source region, a first body region, a drain region, a gate el... | 07/19/2011 |
| 7968924 | Semiconductor device and a method of manufacturing the same In a semiconductor device comprising a capacitive element, an area of the capacitive element is reduced without impairing performance, and further, without addition of an extra step in a manufacturing process. A first capacitor is formed between an active region of ... | 06/28/2011 |
| 7956396 | Memory array having floating gate semiconductor device A method for forming a floating gate semiconductor device such as an electrically erasable programmable read only memory is provided. The device includes a silicon substrate having an electrically isolated active area. A gate oxide, as well as other components of a ... | 06/07/2011 |
| 7952127 | Storage node of stack capacitor and fabrication method thereof A storage node structure includes a substrate having thereon a conductive block region; an etching stop layer covering the conductive block region; a conductive layer penetrating the etching stop layer and electrically connecting the conductive block region; an annu... | 05/31/2011 |
