Class 257/296 - Insulated gate capacitor or insulated gate transistor combined with capacitor (e.g., dynamic memory cell)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: Subject matter wherein the device gate acts as a capacitor
No. of patents: 3341
Last issue date: 03/16/2010

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Number	Title	Issue Date
7679118	Vertical transistor, memory cell, device, system and method of forming same A memory device, system and fabrication method relating to a vertical memory cell including a semiconducting pillar extending outwardly from an integrally connected semiconductor substrate are disclosed. A first source/drain region is formed in the substrate and a b...	03/16/2010
7663172	Vertical memory device and method Method and apparatus are described for a memory cell includes a substrate, a body extending vertically from the substrate, a first gate having a vertical member and a horizontal member and a second gate comprising a vertical member and a horizontal member. The first...	02/16/2010
7652316	Semiconductor transistor (DMOS) device for use as a power amplifier The invention relates to in particular a lateral DMOST with a drain extension (8). In the known transistor a further metal strip (20) is positioned between the gate electrode contact strip and the drain contact (16) which is electrically connect...	01/26/2010
7646051	Semiconductor devices having a bit line plug and methods of fabricating the same A semiconductor device includes a semiconductor substrate, a storage pad and a bit line pad on the semiconductor substrate, a first interlayer insulating layer covering the bit line pad and including a bit line contact hole having a width greater than a width of the...	01/12/2010
7642584	Semiconductor device and method for forming the same A thin-film semiconductor device or integrated circuit comprising an insulating substrate, TFTs (thin-film transistors) formed on the substrate, and multilayer conductive interconnections. The circuit has a first metallization layer becoming gate electrodes and gate...	01/05/2010
7642587	Flat panel display device and method of fabricating the same A flat panel display device including a first region having an organic light emitting diode and a thin film transistor and a second region having a capacitor is disclosed. The capacitor comprises first, second, and third electrodes, where the area of a third capacit...	01/05/2010
7642585	Non-volatile memory cells, memory arrays including the same and methods of operating cells and arrays Memory cells comprising: a semiconductor substrate having a source region and a drain region disposed below a surface of the substrate and separated by a channel region; a tunnel dielectric structure disposed above the channel region, the tunnel dielectric structure...	01/05/2010
7642586	Integrated memory cell array The present invention provides an integrated memory cell array comprising: a semiconductor substrate; a plurality of cell transistor devices including: a pillar formed in said semiconductor substrate; a gate trench surrounding said pillar; a first source/drain regio...	01/05/2010
7638827	Semiconductor memory device A semiconductor memory device capable of preventing bridge formations in a peripheral circuit region includes: a cell region; a peripheral circuit region adjacent to the cell region; and a plurality of line patterns formed in the cell region and the peripheral circu...	12/29/2009
7635886	Semiconductor memory and method for fabricating the semiconductor memory A semiconductor memory is disclosed having an electrically conductive region buried in a substrate, and having an array of first and second cells. The first cells are designed as memory cells each having a selection transistor and a storage capacitor and are connect...	12/22/2009
7633108	Metal/semiconductor/metal current limiter A method is provided for forming a metal/semiconductor/metal (MSM) current limiter and resistance memory cell with an MSM current limiter. The method provides a substrate; forms an MSM bottom electrode overlying the substrate; forms a ZnOx semiconductor layer overly...	12/15/2009
7622759	Semiconductor devices and methods of manufacturing the same A semiconductor device includes a lower conductive layer formed on a semiconductor substrate, an interlayer insulating film that at least substantially covers the lower conductive layer, a plurality of contact holes formed in the interlayer insulating film to expose...	11/24/2009
7619270	Electronic device including discontinuous storage elements An electronic device can include discontinuous storage elements that lie within a trench. The electronic device can include a substrate including a trench that includes a wall and a bottom and extends from a primary surface of the substrate. The electronic device ca...	11/17/2009
7619269	Semiconductor device, manufacturing process thereof and imaging device A semiconductor device including a pixel region in which one or more pixels are formed and a DRAM cell region in which one or more DRAM cells for storing output signals from the pixels are formed, characterized in that the layers constituting the pixel region and th...	11/17/2009
7615815	Cell region layout of semiconductor device and method of forming contact pad using the same A cell region layout of a semiconductor device formed by adding active regions in the outermost portion of a cell region, and a method of forming a contact pad using the same are provided. The layout and the method include a first active region formed at the outermo...	11/10/2009
7612397	Memory cell having first and second capacitors with electrodes acting as control gates for nonvolatile memory transistors A nonvolatile memory cell that can be mounted in a CMOS manufacturing process, and is capable of implementing high level of programming, reading and erasing ability. The memory cell is configured by a MOS transistor including two N-type first impurity diffusion laye...	11/03/2009
7608876	Merged MOS-bipolar capacitor memory cell A high density vertical merged MOS-bipolar-capacitor gain cell is realized for DRAM operation. The gain cell includes a vertical MOS transistor having a source region, a drain region, and a floating body region therebetween. The gain cell includes a vertical bi-pola...	10/27/2009
7608878	Semiconductor device manufactured with a double shallow trench isolation process A method for manufacturing a semiconductor device includes forming a device isolation film by a double Shallow Trench Isolation (STI) process, forming a first active region having a negative slope and a second active region having a positive slope. Additionally, the...	10/27/2009
7608877	Circuit device having capacitor and field effect transistor, and display apparatus therewith In a circuit device having a field effect transistor and a capacitor, the capacitor is connected to at least one of a gate electrode, a source electrode and a drain electrode of a field effect transistor, the field effect transistor has a channel comprised of a firs...	10/27/2009
7608879	Semiconductor device including a capacitance It is an object to obtain a semiconductor device including a capacitance having a great Q-value. In an SOI substrate comprising a support substrate (165), a buried oxide film (166) and an SOI layer (171), an isolating oxide film 167 (1...	10/27/2009
7605418	Methods of fabricating capacitor A fabricating method of a capacitor is disclosed. Particularly, a fabricating method of a capacitor which forms a capacitor in the place where the insulation layer of an STI region is removed, preventing interlayer dielectric layers from becoming thick. A disclosed ...	10/20/2009
7602001	Capacitorless one transistor DRAM cell, integrated circuitry comprising an array of capacitorless one transistor DRAM cells, and method of forming lines of capacitorless one transistor DRAM cells This invention includes a capacitorless one transistor DRAM cell that includes a pair of spaced source/drain regions received within semiconductive material. An electrically floating body region is disposed between the source/drain regions within the semiconductive ...	10/13/2009
7598558	Method of manufacturing semiconductor integrated circuit device having capacitor element In a complete CMOS SRAM having a memory cell composed of six MISFETs formed over a substrate, a capacitor element having a stack structure is formed of a lower electrode covering the memory cell, an upper electrode, and a capacitor insulating film (dielectric film) ...	10/06/2009
7598557	Semiconductor device and method for fabricating a semicondutor device including first and second hydrogen diffusion preventing films The semiconductor device comprises a first insulation film 26 formed over a semiconductor substrate 10, first conductor plug 32 buried in a first contact hole 28a formed down to a source/drain diffused layer 22, a capacitor ...	10/06/2009
7595521	Terraced film stack A process and apparatus directed to forming a terraced film stack of a semiconductor device, for example, a DRAM memory device, is disclosed. The present invention addresses etch undercut resulting from materials of different etch selectivity used in the film stack,...	09/29/2009
7592658	Method of forming a semiconductor device having a capacitor and a resistor A semiconductor device comprising the following. A structure having: a capacitor; a first resistor; and a second resistor each within at least a portion of an oxide structure and a metal-oxide semiconductor electrode not within at least a portion of the oxide struct...	09/22/2009
7589368	Three-dimensional memory devices Memory devices are disclosed. One example of a memory device may include two layers of memory arrays each containing at least four memory cells. In particular, the memory device includes two word lines commonly shared by the two layers of the memory arrays, with the...	09/15/2009
7589367	Layout structure in semiconductor memory device comprising global work lines, local work lines, global bit lines and local bit lines A line layout structure and method in a semiconductor memory device having a hierarchical structure are provided. In a semiconductor memory device having a global word line and a local word line, and a global bit line and a local bit line, and individually disposing...	09/15/2009
7589369	Semiconductor constructions The invention includes a method in which a semiconductor substrate is provided to have a memory array region, and a peripheral region outward of the memory array region. Paired transistors are formed within the memory array region, with such paired transistors shari...	09/15/2009
7582925	Integrated circuit devices including insulating support layers An integrated circuit device may include a substrate, a plurality of storage electrode landing pads on the substrate, and a plurality of storage electrodes. Each of the plurality of storage electrodes may be on a portion of a respective one of the plurality of stora...	09/01/2009
7582924	Semiconductor devices having polymetal gate electrodes Semiconductor devices and methods of fabricating the same are provided. A gate insulating film is provided on a semiconductor substrate. A polymetal gate electrode is provided on the gate insulating film. The polymetal gate electrode includes a conductive polysilico...	09/01/2009
7576379	Floating body dynamic random access memory with enhanced source side capacitance A floating body dynamic random access memory (DRAM) structure has a shallow source (first source portion) and a deep source (second source portion), of which the deep source is thicker. A portion of the floating body extends beneath the shallow source to provide ext...	08/18/2009
7573085	Deep trench formation in semiconductor device fabrication A semiconductor structure. The structure includes (a) a semiconductor substrate; (b) a hard mask layer on top of the semiconductor substrate; and (c) a hard mask layer opening in the hard mask layer. The semiconductor substrate is exposed to the atmosphere through t...	08/11/2009
7569877	System and method based on field-effect transistors for addressing nanometer-scale devices A system and method for selecting nanometer-scaled devices. The method includes a plurality of semiconductor wires. Two adjacent semiconductor wires of the plurality of semiconductor wires are associated with a separation smaller than or equal to 100 nm. Additionall...	08/04/2009
7564084	Dual-gate dynamic random access memory device having vertical channel transistors and method of fabricating the same A dynamic random access memory (DRAM) device has dual-gate vertical channel transistors. The device is comprised of pillar-shaped active patterns including source regions contacting with a semiconductor substrate, drain regions formed over the drain regions, and cha...	07/21/2009
7564085	Mechanical memory device and method of manufacturing the same A memory device that performs writing and reading operations using a mechanical movement of a nanowire, and a method of manufacturing the memory device are provided. The memory device includes a source electrode, a drain electrode, and a gate electrode, each of whic...	07/21/2009
RE40842	Memory elements and methods for making same Annular, linear, and point contact structures are described which exhibit a greatly reduced susceptibility to process deviations caused by lithographic and deposition variations than does a conventional circular contact plug. In one embodiment, a standard conductive...	07/14/2009
7554147	Memory device and manufacturing method thereof A memory device in which both DRAM and phase-change memory (PCRAM) are mounted is provided with a DRAM bit line, a PCRAM bit line or a PCRAM source line formed on an conductive layer shared with the DRAM bit line, and a sense amplifier connected between the DRAM bit...	06/30/2009
7554146	Metal-insulator-metal capacitor and method of fabricating the same In a metal-insulator-metal (MIM) capacitor and a method of fabricating the MIM capacitor, a metal-insulator-metal (MIM) capacitor comprises: a lower electrode pattern which is formed on a substrate and includes a conductive layer having a portion as a lower intercon...	06/30/2009
7547935	Semiconductor devices including buried digit lines that are laterally offset from corresponding active-device regions A method of electrically linking contacts of a semiconductor device to their corresponding digit lines. The method includes disposing a quantity of mask material into a trench through which the contact is exposed. The mask also abuts a connect region of a conductive...	06/16/2009

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Class 257/296 - Insulated gate capacitor or insulated gate transistor combined with capacitor (e.g., dynamic memory cell)