Celebrity Inventors
Mark Twain (Samuel L. Clemens) received Patent No. 121,992 for "An Improvement in Adjustable and Detachable Straps for Garments." He later received two more patents: one for a self-pasting scrapbook and one for a game to help players remember important historical dates.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 8445893 | High-performance gate oxides such as for graphene field-effect transistors or carbon nanotubes An apparatus or method can include forming a graphene layer including a working surface, forming a polyvinyl alcohol (PVA) layer upon the working surface of the graphene layer, and forming a dielectric layer upon the PVA layer. In an example, the PVA layer can be ac... | 05/21/2013 |
| 8436337 | Amorphous multi-component metallic thin films for electronic devices An electronic structure comprising: (a) a first metal layer; (b) a second metal layer; (c) and at least one insulator layer located between the first metal layer and the second metal layer, wherein at least one of the metal layers comprises an amorphous multi-compon... | 05/07/2013 |
| 8410474 | Graphene grown substrate and electronic/photonic integrated circuits using same A substrate having a graphene film grown thereon according to the present invention includes: a base substrate; a patterned aluminum oxide film formed on the base substrate, the patterned aluminum oxide film having an average composition of Al2−xO3... | 04/02/2013 |
| 8389978 | Two-shelf interconnect Consistent with the present disclosure, a package is provided that includes a housing having a recessed portion to accommodate an integrated circuit or chip. The housing has an inner periphery that defines or delineates the recessed portion. The inner periphery may ... | 03/05/2013 |
| 8378335 | Semiconductor device and method for fabricating the same A semiconductor device according to an embodiment, includes a catalytic metal film, a graphene film, a contact plug, and an adjustment film. The catalytic metal film is formed above a substrate. The graphene film is formed on the catalytic metal film. The contact pl... | 02/19/2013 |
| 8288760 | Field effect transistor, integrated circuit element, and method for manufacturing the same A field effect transistor of an embodiment of the present invention includes, a semiconductor substrate containing Si atoms; a protruding structure formed on the semiconductor substrate; a channel region formed in the protruding structure and containing Ge atoms; an... | 10/16/2012 |
| 8227794 | Complementary logic gate device Provided is a complementary logical gate device represented by a silicon CMOS logical circuit among semiconductor integrated logical circuits which can effectively solve the problem of the speed performance limit of an ultra-large scale integration and an ultra-low ... | 07/24/2012 |
| 8120016 | Imaging device A solid-state imaging device, a line sensor and an optical sensor for enhancing a wide dynamic range while keeping high sensitivity with a high S/N ratio, and a method of operating a solid-state imaging device for enhancing a wide dynamic range while keeping high se... | 02/21/2012 |
| 8106383 | Self-aligned graphene transistor A graphene field effect transistor includes a gate stack, the gate stack including a seed layer, a gate oxide formed over the seed layer, and a gate metal formed over the gate oxide; an insulating layer; and a graphene sheet displaced between the seed layer and the ... | 01/31/2012 |
| 7999251 | Nanowire MOSFET with doped epitaxial contacts for source and drain A FET structure with a nanowire forming the FET channel, and doped source and drain regions formed by radial epitaxy from the nanowire body is disclosed. A top gated and a bottom gated nanowire FET structures are discussed. The source and drain fabrication can use e... | 08/16/2011 |
| 7999252 | Image sensor and method for fabricating the same An image sensor includes an epi-layer of a first conductivity type formed in a substrate, a photodiode formed in the epi-layer, and a first doping region of a second conductivity type formed under the photodiode to separate the first doping region from the photodiod... | 08/16/2011 |
| 7851785 | Magnetic tunnel transistor with thin read gap for head applications A magnetic tunnel transistor (MTT) for a disk drive read head includes a barrier of TiO disposed between a ferromagnetic collector and a ferromagnetic base for preferentially selecting only “hot” electrons for propagation to the collector. ... | 12/14/2010 |
| 7728324 | Field effect transistor, integrated circuit element, and method for manufacturing the same A field effect transistor of an embodiment of the present invention includes, a semiconductor substrate containing Si atoms; a protruding structure formed on the semiconductor substrate; a channel region formed in the protruding structure and containing Ge atoms; an... | 06/01/2010 |
| 7629604 | Nano-based device and method A nano-based device includes a support structure providing a support surface, a second structure providing a second surface angled with respect to the support surface, and at least one nano-emitter provided on the second surface. ... | 12/08/2009 |
| 7576353 | Ballistic deflection transistor and logic circuits based on same A quantum well is formed in a substrate to define a hub, ports extending from the hub, and a deflective structure in the hub. Electrons move through the hub and ports according to the ballistic electron effect. Gates control the movement of the electrons, causing th... | 08/18/2009 |
| 7504654 | Structure for logical “OR” using ballistics transistor technology A ballistic logic gate is disclosed. The ballistic logic gate may include an etched silicon substrate with a pair of etched silicon triangular baffles defining input channels. An electron may travel through the input channels toward a nano-deflector with a parabolic... | 03/17/2009 |
| 7432522 | Nanowhiskers with pn junctions, doped nanowhiskers, and methods for preparing them Nano-engineered structures are disclosed, incorporating nanowhiskers of high mobility conductivity and incorporating pn junctions. In one embodiment, a nanowhisker of a first semiconducting material has a first band gap, and an enclosure comprising at least one seco... | 10/07/2008 |
| 7414262 | Electronic devices and methods for forming the same Electronic devices, such as those having a flexible substrate and printed material on the flexible substrate. In one embodiment, the printed material and substrate are part of an electronic device having at least three terminals, wherein the electronic device has a ... | 08/19/2008 |
| 7361973 | Embedded stressed nitride liners for CMOS performance improvement The present invention provides a semiconducting device including a gate region positioned on a mesa portion of a substrate; and a nitride liner positioned on the gate region and recessed surfaces of the substrate adjacent to the gate region, the nitride liner provid... | 04/22/2008 |
| 7332737 | Isolation trench geometry for image sensors A pixel cell including a substrate having a top surface. A photo-conversion device is at a surface of the substrate and a trench is in the substrate adjacent the photo-conversion device. The trench has sidewalls and a bottom. At least one sidewall is angled less tha... | 02/19/2008 |
| 7321155 | Offset spacer formation for strained channel CMOS transistor A strained channel transistor and method for forming the same, the strained channel transistor including a semiconductor substrate; a gate dielectric overlying a channel region; a gate electrode overlying the gate dielectric; source drain extension (SDE) regions and... | 01/22/2008 |
| 7315041 | Switching devices based on half-metals One embodiment of the present invention provides a switching device that can vary a spin-polarized current based on an input signal. The switching device comprises a first conducting region, a second conducting region, and a half-metal region interposed between the ... | 01/01/2008 |
| 7303948 | Semiconductor device including MOSFET having band-engineered superlattice A semiconductor device includes a substrate, and at least one MOSFET adjacent the substrate. The MOSFET may include a superlattice channel that, in turn, includes a plurality of stacked groups of layers. The MOSFET may also include source and drain regions laterally... | 12/04/2007 |
| 7288457 | Method for making semiconductor device comprising a superlattice with upper portions extending above adjacent upper portions of source and drain regions A method for making a semiconductor device may include providing a semiconductor substrate and forming at least one MOSFET by forming spaced apart source and drain regions and a superlattice on the substrate so that the superlattice is between the source and drain r... | 10/30/2007 |
| 7279699 | Integrated circuit comprising a waveguide having an energy band engineered superlattice An integrated circuit may include at least one active optical device and a waveguide coupled thereto. The waveguide may include a superlattice including a plurality of stacked groups of layers. Each group of layers of the superlattice may include a plurality of stac... | 10/09/2007 |
| 7279701 | Semiconductor device comprising a superlattice with upper portions extending above adjacent upper portions of source and drain regions A semiconductor device may include a semiconductor substrate and at least one metal oxide semiconductor field-effect transistor (MOSFET). The MOSFET may include spaced apart source and drain regions on the semiconductor substrate, and a superlattice including a plur... | 10/09/2007 |
| 7268399 | Enhanced PMOS via transverse stress In the present invention, a PMOS device comprises a channel region formed in {100} silicon with first and second source/drain region disposed on either side of the channel region. The channel region is oriented such that a current flow between the source/drain regio... | 09/11/2007 |
| 7265002 | Method for making a semiconductor device including a MOSFET having a band-engineered superlattice with a semiconductor cap layer providing a channel A method for making a semiconductor device may include providing a substrate, and forming at least one MOSFET adjacent the substrate by forming a superlattice including a plurality of stacked groups of layers and a semiconductor cap layer on an uppermost group of la... | 09/04/2007 |
| 7229902 | Method for making a semiconductor device including a superlattice with regions defining a semiconductor junction A method for making a semiconductor device may include forming a superlattice comprising a plurality of stacked groups of layers. Each group of layers of the superlattice may include a plurality of stacked base silicon monolayers defining a base silicon portion and ... | 06/12/2007 |
| 7227174 | Semiconductor device including a superlattice and adjacent semiconductor layer with doped regions defining a semiconductor junction A semiconductor device may include a superlattice comprising a plurality of stacked groups of layers. Each group of layers of the superlattice may include a plurality of stacked base silicon monolayers defining a base silicon portion and an energy band-modifying lay... | 06/05/2007 |
| 7202494 | FINFET including a superlattice A semiconductor device may include at least one fin field-effect transistor (FINFET) comprising a fin, source and drain regions adjacent opposite ends of the fin, and a gate overlying the fin. The fin may include at least one superlattice including a plurality of st... | 04/10/2007 |
| 7202511 | Near-infrared visible light photon counter Electromagnetic energy is detected with high efficiency in the spectral range having wavelengths of about 1–2 microns by coupling an absorber layer having high quantum efficiency in the spectral range having wavelengths of about 1–2 microns to an intrinsic semic... | 04/10/2007 |
| 7173275 | Thin-film transistors based on tunneling structures and applications A hot electron transistor includes an emitter electrode, a base electrode, a collector electrode, and a first tunneling structure disposed and serving as a transport of electrons between the emitter and base electrodes. The first tunneling structure includes at leas... | 02/06/2007 |
| 7153763 | Method for making a semiconductor device including band-engineered superlattice using intermediate annealing A method for making a semiconductor device may include forming a superlattice including a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at le... | 12/26/2006 |
| 7151054 | Semiconductor processing methods of forming and utilizing antireflective material layers, and methods of forming transistor gate stacks In one aspect, the invention includes a semiconductor processing method comprising exposing silicon, nitrogen and oxygen in gaseous form to a high density plasma during deposition of a silicon, nitrogen and oxygen containing solid layer over a substrate. In a... | 12/19/2006 |
| 7122735 | Quantum well energizing method and apparatus A method and apparatus that converts energy provided by a chemical reaction into energy for charging a quantum well device. The disclosed apparatus comprises a catalyst layer that catalyzes a chemical reaction and captures hot electrons and hot phonons generated by ... | 10/17/2006 |
| 7123792 | Configurable aperiodic grating device The invention relates to the field of grating structures. The invention provides a longitudinal grating having an aperiodic structure, wherein the grating has a selected response characteristic and any repeated unit cell in the structure is significantly longer than... | 10/17/2006 |
| 7109052 | Method for making an integrated circuit comprising a waveguide having an energy band engineered superlattice A method for making an integrated circuit may include forming at least one active optical device and a waveguide coupled thereto. The waveguide may include a superlattice including a plurality of stacked groups of layers. Each group of layers of the superlattice may... | 09/19/2006 |
| 7101739 | Method for forming a schottky diode on a silicon carbide substrate A method for manufacturing a vertical Schottky diode with a guard ring on a lightly-doped N-type silicon carbide layer, including forming a P-type epitaxial layer on the N-type layer; implanting N-type dopants in areas of the P-type epitaxial layer to neutralize in ... | 09/05/2006 |
| 7071119 | Method for making a semiconductor device including band-engineered superlattice having 3/1-5/1 germanium layer structure A semiconductor device includes a superlattice that, in turn, includes a plurality of stacked groups of layers. The device may also include regions for causing transport of charge carriers through the superlattice in a parallel direction relative to the stacked grou... | 07/04/2006 |
