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| Number | Title | Issue Date |
| 8039879 | Semiconductor device having a control circuit and method of its manufacture A semiconductor has an IGBT active section and a control circuit section for detecting an IGBT abnormal state. A collector region is formed on the back surface side (i.e., on the IGBT collector side) in a selective manner, namely right under the IGBT active section.... | 10/18/2011 |
| 7898008 | Vertical-type, integrated bipolar device and manufacturing process thereof A bipolar device is integrated in an active layer, wherein delimitation trenches surround respective active areas housing bipolar transistors of complementary types. Each active area accommodates a buried layer; a well region extending on top of the buried layer; a ... | 03/01/2011 |
| 7800143 | Dynamic random access memory with an amplified capacitor A memory cell and methods of making and operating the same are provided. In one aspect, a method of forming a memory cell is provided that includes forming a MOS transistor that has a gate, a source region and a drain region. A bipolar transistor is formed that has ... | 09/21/2010 |
| 7781808 | Semiconductor apparatus and complimentary MIS logic circuit A configuration is adopted comprising an NchMOS transistor 1 equipped with an insulating isolation layer 4 providing insulation and isolation using an SOI structure, and a capacitor formed using an insulating film, with a silicon substrate B being made... | 08/24/2010 |
| 7759711 | Semiconductor device with substrate having increased resistance due to lattice defect and method for fabricating the same Disclosed is a semiconductor device including: an N-type RESURF region formed in a P-type semiconductor substrate; a P-type base region formed in an upper portion of the semiconductor substrate so as to be adjacent to the RESURF region; an N-type emitter/source regi... | 07/20/2010 |
| 7535040 | Insulated gate semiconductor device and method for manufacturing same In an insulated gate semiconductor device (1) having an N− type base region (11), P+ type collector regions (12), P type base regions (13), and N+ type emitter regions (14), an N+ type ... | 05/19/2009 |
| 7422952 | Method of forming a BJT with ESD self protection A ballasting region is placed between the base region and the collector contact of a bipolar junction transistor to relocate a hot spot away from the collector contact of the transistor. Relocating the hot spot away from the collector contact prevents the collector ... | 09/09/2008 |
| 7414298 | Super self-aligned collector device for mono-and hetero bipolar junction transistors, and method of making same The invention relates to a process of forming a compact bipolar junction transistor (BJT) that includes forming a self-aligned collector tap adjacent the emitter stack and an isolation structure. A base layer is formed from epitaxial silicon that is disposed in the ... | 08/19/2008 |
| 7385236 | BiFET semiconductor device having vertically integrated FET and HBT The invention provides a BiFET semiconductor device vertically integrating a FET and a HBT on the same substrate. The BiFET semiconductor device comprises a HBT structure, a high-resistivity structure, and a FET structure, sequentially formed in this order from bott... | 06/10/2008 |
| 7323728 | Semiconductor device Disclosed is a semiconductor device including an n+-type semiconductor layer formed on a substrate, a first n-type semiconductor layer formed on the n+-type semiconductor layer, a p-type semiconductor layer formed on the first n-type semiconduc... | 01/29/2008 |
| 7285469 | Bipolar method and structure having improved BVCEO/RCS trade-off made with depletable collector columns In accordance with the invention, there are various methods of making an integrated circuit comprising a bipolar transistor. According to an embodiment of the invention, the bipolar transistor can comprise a substrate, a collector comprising a plurality of alternati... | 10/23/2007 |
| 7271428 | Heterojunction bipolar transistor The invention provides a heterojunction bipolar transistor comprising a substrate having a collector therein, an intrinsic base region, a first extrinsic base region, a second extrinsic base region, an emitter on the intrinsic base layer and a spacer adjacent the em... | 09/18/2007 |
| 7229407 | Capsule endoscope with electroluminescence light source A capsule endoscope includes a capsule portion. The capsule portion includes at least an observation optical unit having an image pick-up element and an optical lens that forms an objective optical system, an illuminating unit having an illuminating substrate, an el... | 06/12/2007 |
| 7227197 | Semiconductor high-voltage devices A semiconductor high-voltage device comprising a voltage sustaining layer between a n+-region and a p+-region is provided, which is a uniformly doped n(or p)-layer containing a plurality of floating p (or n)-islands. The effect of the floating islands is to absorb a... | 06/05/2007 |
| 7221021 | Method of forming high voltage devices with retrograde well A high voltage device with retrograde well is disclosed. The device comprises a substrate, a gate region formed on the substrate, and a retrograde well placed in the substrate next to the gate region, wherein the retrograde well reduces a dopant concentration on the... | 05/22/2007 |
| 7205587 | Semiconductor device and method of producing the same A method of producing a semiconductor device includes the steps of: preparing a double SOI substrate, forming a deep trench, filling the deep trench, forming an opening, forming a cavity, depositing a polycrystalline silicon layer, and forming a bipolar transistor. | 04/17/2007 |
| 7195959 | Thyristor-based semiconductor device and method of fabrication A thyristor-based semiconductor memory device may comprise at least a region thereof, e.g., a p-base region, having high ionization energy impurity, such as a dopant. This high ionization energy impurity within a base region may be operable to compensate for a gain-... | 03/27/2007 |
| 7145206 | MOS field effect transistor with reduced parasitic substrate conduction A MOS field effect transistor includes an auxiliary diffusion formed in the drain region where the auxiliary diffusion has a conductivity type opposite to the drain region and is electrically shorted to the drain region. The auxiliary diffusion region forms a parasi... | 12/05/2006 |
| 7119369 | FET having epitaxial silicon growth A field-effect transistor has a channel region in a bulk semiconductor substrate, a first source/drain region on a first side of the channel region, a second source/drain region on a second side of the channel region, and an extension of epitaxial monocrystalline ma... | 10/10/2006 |
| 7095101 | Supporting frame for surface-mount diode package A supporting frame is used to solidly bridge to the two metallic contacts of a surface mount diode chip. Any bending or twisting stress between the two contacts is borne by the supporting frame instead of the diode chip. Otherwise the stress may damage the diode chi... | 08/22/2006 |
| 7084455 | Power semiconductor device having a voltage sustaining region that includes terraced trench with continuous doped columns formed in an epitaxial layer A method is provided for forming a power semiconductor device. The method begins by providing a substrate of a first conductivity type and forming a voltage sustaining region on the substrate. The voltage sustaining region is formed in the following manner. First, a... | 08/01/2006 |
| 7064415 | Self-aligned bipolar transistor having increased manufacturability According to one exemplary embodiment, a bipolar transistor comprises a base having a top surface. The bipolar transistor further comprises a base oxide layer situated on top surface of the base. The bipolar transistor further comprises a sacrificial post situated o... | 06/20/2006 |
| 7034616 | Operational amplification circuit, overheat detecting circuit and comparison circuit In a circuit according to the present invention, a multi-collector transistor is provided which includes first to third collectors so that, when a current does not flow from the second collector, a current from the first collector increases but a current from the th... | 04/25/2006 |
| 7026666 | Self-aligned NPN transistor with raised extrinsic base A self-aligned bipolar transistor and a method of formation thereof are provided. The bipolar transistor has a raised extrinsic base such that the link base resistance is reduced by providing an extrinsic base which is thicker than the intrinsic base. The increase i... | 04/11/2006 |
| 7015519 | Structures and methods for fabricating vertically integrated HBT/FET device Methods and systems for fabricating integrated pairs of HBT/FET's are disclosed. One preferred embodiment comprises a method of fabricating an integrated pair of GaAs-based HBT and FET. The method comprises the steps of: growing a first set of epitaxial layers for f... | 03/21/2006 |
| 7005712 | Method for manufacturing a semiconductor device A semiconductor device of the present invention includes a semiconductor layer 10, an insulation gate type heavy insulated transistor 200 and an insulation gate type light insulated transistor 300 having different drain-source breakdown voltages... | 02/28/2006 |
| 6993298 | Programmable controller with RF wireless interface A programmable logic controller has a wireless communication interface. A radio frequency identification chip set is mounted to, and is in communication with, the active elements of an integrated circuit on one or more circuit boards in the programmable controller. ... | 01/31/2006 |
| 6992338 | CMOS transistor spacers formed in a BiCMOS process According to an exemplary method in one embodiment, a transistor gate is fabricated on a substrate. Next, an etch stop layer may be deposited on the substrate. The etch stop layer may, for example, be TEOS silicon dioxide. Thereafter, a conformal layer is deposited ... | 01/31/2006 |
| 6979845 | Semiconductor device in which punchthrough is prevented A semiconductor device includes a semiconductor region of a first conductive type. First and second regions of a second conductive type opposite to the first conductive type are provided in a surface of the semiconductor region in a predetermined interval. A third r... | 12/27/2005 |
| 6960797 | Semiconductor device The object of the present invention is to provide a semiconductor device, which is suitable for use to connect electric condenser microphones. A semiconductor device, comprises: a conductivity-type substrate; an epitaxial layer formed on top of the substrate; island... | 11/01/2005 |
| 6956266 | Structure and method for latchup suppression utilizing trench and masked sub-collector implantation A method and structure for an integrated circuit comprising a substrate of a first polarity; a trench structure in the substrate; a well region of a second polarity abutting the trench structure; and a heavily doped region of the second polarity abutting the trench ... | 10/18/2005 |
| 6949764 | Fully-depleted-collector silicon-on-insulator (SOI) bipolar transistor useful alone or in SOI BiCMOS A bipolar transistor structure is described incorporating an emitter, base, and collector having a fully depleted region on an insulator of a Silicon-On-Insulator (SOI) substrate without the need for a highly doped subcollector to permit the fabrication of vertical ... | 09/27/2005 |
| 6943611 | Drive control circuit for a junction field-effect transistor A drive control circuit for a junction field-effect transistor having a gate terminal, a drain terminal and a source terminal as well as a gate leakage current and a maximally permissible gate current, includes a current supply which feeds the gate and produces a co... | 09/13/2005 |
| 6939736 | Ideal operational amplifier layout techniques for reducing package stress and configurations therefor A method of reducing package stress includes placing matched components of an op-amp substantially in a region of a die having the least stress gradients. The region is located in the center of the die. Further, the center is the common centroid of the die. The matc... | 09/06/2005 |
| 6936867 | Semiconductor high-voltage devices A semiconductor high-voltage device comprising a voltage sustaining layer between a n+-region and a p+-region is provided, which is a uniformly doped n(or p)-layer containing a plurality of floating p (or n)-islands. The effect of the floating islands is to absorb a... | 08/30/2005 |
| 6933205 | Integrated circuit device and method of manufacturing the same The present invention provides an integrated circuit, comprising a semiconductor substrate, an active element formed on the side of one main surface of the semiconductor substrate, an insulating region formed on the side of the main surface of the semiconductor subs... | 08/23/2005 |
| 6927460 | Method and structure for BiCMOS isolated NMOS transistor A structure of and a method for making an isolated NMOS transistor using standard BiCMOS processing steps and techniques. No additional masks and processing steps are needed for the isolated NMOS device relative to the standard process flow. A P-type substrate with ... | 08/09/2005 |
| 6911681 | Method of base formation in a BiCMOS process Disclosed is a bipolar complementary metal oxide semiconductor (BiCMOS) or NPN/PNP device that has a collector, an intrinsic base above the collector, shallow trench isolation regions adjacent the collector, a raised extrinsic base above the intrinsic base, a T-shap... | 06/28/2005 |
| 6911715 | Bipolar transistors and methods of manufacturing the same A bipolar transistor in which the occurrence of Kirk effect is suppressed when a high current is injected into the bipolar transistor and a method of fabricating the bipolar transistor are described. The bipolar transistor includes a first collector region of a firs... | 06/28/2005 |
| 6906359 | BiFET including a FET having increased linearity and manufacturability According to one exemplary embodiment, a BiFET situated on a substrate comprises an emitter layer segment situated over the substrate, where the emitter layer segment comprises a semiconductor of a first type. The HBT further comprises a first segment of an etch sto... | 06/14/2005 |
