Class 257/269 - With means to adjust barrier height (e.g., doping profile)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: Subject matter including means to adjust the electronic
No. of patents: 35
Last issue date: 05/25/2010

Number	Title	Issue Date
7723758	Method for dopant calibration of delta doped multilayered structure In a calibration method, the relation between dopant concentrations of δ-doping layers in a multilayered semiconductor structure and process parameters is determined S1 based on multiple bulk specimens of the material in which the δ-doping layers are locate...	05/25/2010
7417270	Distributed high voltage JFET A Junction Field Effect Transistor (JFET) can be fabricated with a well region that include a channel region having an average dopant concentration substantially less the average doping concentration of the remaining portions of the well region. The lower average do...	08/26/2008
7326975	Buried channel type transistor having a trench gate and method of manufacturing the same In a method of manufacturing a buried channel type transistor, a trench is formed at a surface portion of a substrate. A first and a second threshold voltage control regions are formed at portions of the substrate beneath a bottom face of the trench and adjacent to ...	02/05/2008
7304329	Field effect transistor A field effect transistor includes a semiconductor substrate having an active region, a source region, and a drain region at an upper portion of the substrate. The active region is located between the source and drain regions. A gate electrode is located on the acti...	12/04/2007
7301180	Structure and method for a high-speed semiconductor device having a Ge channel layer The invention provides semiconductor structure comprising a strained Ge channel layer, and a gate dielectric disposed over the strained Ge channel layer. In one aspect of the invention, a strained Ge channel MOSFET is provided. The strained Ge channel MOSFET include...	11/27/2007
7226803	Photodiode with ultra-shallow junction for high quantum efficiency CMOS image sensor and method of formation A pinned photodiode with an ultra-shallow highly-doped surface layer of a first conductivity type and a method of formation are disclosed. The ultra-shallow highly-doped surface layer has a thickness of about 100 Angstroms to about 500 Angstroms and a dopant concent...	06/05/2007
7078776	Low threshold voltage semiconductor device A semiconductor device has a first semiconductor region formed in a semiconductor substrate and having a first conductivity type due to first-conductivity-type active impurities contained in the first semiconductor region, and a second semiconductor region formed be...	07/18/2006
6972234	High voltage MOS devices with high gated-diode breakdown voltage and punch-through voltage A method of fabricating CMOS devices suitable for high voltage and low voltage applications, while maintaining minimum channel lengths for the devices. In one embodiment, pocket implants (310) are formed in a minimum channel device causing a reverse channel e...	12/06/2005
6960499	Dual-counterdoped channel field effect transistor and method A field effect transistor with a dual-counterdoped channel is disclosed. The transistor features a channel comprising a first doped region (28) and a second doped region (26) underlying the first doped region. A source and drain (32) are formed ...	11/01/2005
6870189	Pinch-off type vertical junction field effect transistor and method of manufacturing the same A junction field effect transistor (JFET) is provided that is capable of a high voltage resistance, high current switching operation, that operates with a low loss, and that has little variation. This JFET is provided with a gate region (2) of a second conduc...	03/22/2005
6693331	Method of fabricating dual threshold voltage n-channel and p-channel MOSFETS with a single extra masked implant operation A method of forming an MOS integrated circuit having at least two types of NFET, each type having a different threshold voltage, and at least two types of PFET, each type having a different threshold voltage, includes forming at least four active regions ...	02/17/2004
6566696	Self-aligned VT implant Integrated circuits with transistors exhibiting improved junction capacitances and various methods of fabricating the same are provided. In one aspect, a method of manufacturing is provided that includes forming a doped region in an active area of a subst...	05/20/2003
6521961	Semiconductor device using a barrier layer between the gate electrode and substrate and method therefor An enhancement mode semiconductor device has a barrier layer disposed between the gate electrode of the device and the semiconductor substrate underlying the gate electrode. The barrier layer increases the Schottky barrier height of the gate electrode-bar...	02/18/2003
6365919	Silicon carbide junction field effect transistor A lateral silicon carbide junction field effect transistor has p-conductive and n-conductive silicon carbide layers. The layers are provided in pairs in lateral direction in a silicon carbide body. Trenches for a source, a drain and a gate extend from a p...	04/02/2002
6329704	Ultra-shallow junction dopant layer having a peak concentration within a dielectric layer A process for forming an ultra-shallow junction depth, doped region within a silicon substrate. The process includes forming a dielectric film on the substrate, then implanting an ionic dopant species into the structure. The profile of the implanted speci...	12/11/2001
6180959	Static induction semiconductor device, and driving method and drive circuit thereof In a silicon carbide static induction transistor, at a surface part of a semiconductor substrate, a p-type gate region is formed partially overlapping a n-type source region, whereby the high accuracy in alignment between the gate region and the source re...	01/30/2001
6037203	Method of fabricating a semiconductor device having triple well structure The present invention discloses a semiconductor device having a triple well structure. The semiconductor device includes a N-type impurity doped buried layer, formed in the semiconductor substrate at a predetermined depth from the surface of the first act...	03/14/2000
5962893	Schottky tunneling device An n-semiconductor layer is arranged on a low-resistance n-substrate. A drain electrode is in ohmic contact with the n-substrate. A source electrode forms a Schottky junction with the n-semiconductor layer. A gate electrode is arranged adjacent to the sou...	10/05/1999
5939757	Semiconductor device having triple well structure The present invention discloses a semiconductor device having a triple well structure. The semiconductor device includes a N-type impurity doped buried layer, formed in the semiconductor substrate at a predetermined depth from the surface of the first act...	08/17/1999
5814832	Electron emitting semiconductor device An electron emitting semiconductor device is provided with a P-type semiconductor layer arranged on a semiconductor substrate having an impurity concentration. A Schottky barrier electrode is arranged on a surface of the P-type semiconductor layer. Plural...	09/29/1998
5532505	Field effect transistor including a cap with a doped layer formed therein This invention aims at providing an high output FET having a planar type-gate structure suitable for integration, and a structure that suppresses long gate effect. A heavily doped thin channel layer 13 is formed on a semiconductor substrate 11, and a cap ...	07/02/1996
5462888	Process for manufacturing semiconductor BICMOS device A process for fabricating transistors on a substrate is disclosed. In accordance with the process, stacks of material are formed on the surface of the substrate. Walls of silicon dioxide are created around the stacks in order to insulate the material with...	10/31/1995
5401987	Self-cascoding CMOS device A self-cascoding transconductance circuit has cascoding and current sink/source FETs, serially connected with their gates tied together to receive an input voltage, wherein the cascoding FET has a threshold voltage having an absolute value at least 0.1 vo...	03/28/1995
5396132	MESFET mixer circuit having a pulse doped structure An FET mixer circuit having a stable input impedance uses two tandem-connected GaAs MESFET's (1) and (2) of pulse doped structure instead of a conventional MESFET or a HEMT, as an active device. A gate biasing point for the FET (1) is set around a pinch-o...	03/07/1995
5369294	Field effect transistor and method of fabricating A junction field effect transistor, specifically a static induction transistor. The N-type source regions are formed as two zones. First, relatively lightly doped first zones are formed by ion-implanting doping material relatively deeply into the semicond...	11/29/1994
5338949	Semiconductor device having series-connected junction field effect transistors A JFET configuration is obtained whose pinch-off voltage can be set by means of mask dimensions, without process changes, and which is at the same time suitable for operation at very low and very high voltages by cascoding of a first JFET with a diffused ...	08/16/1994
5101254	Schottky barrier semiconductor photodetector including graded energy band gap layer A semiconductor photodetector includes a semiconductor layer disposed on a main surface of a first conductivity type semiconductor substrate and a metal layer producing a Schottky junction with the semiconductor layer disposed on a main surface of the sem...	03/31/1992
4984049	Static induction thyristor A static induction thyristor having a mesh like gate region in front of the cathode, and between the gate region and the cathode a high resistance region having effective impurity concentration of 1011 cm-3 -5×1014 cm	01/08/1991
4590502	Camel gate field effect transistor device The disclosed device is a field-effect transistor which includes a support region that may typically comprise a substrate having a buffer layer thereon. A semiconductor channel layer of one conductivity type is disposed on the support region. A first high...	05/20/1986
4486766	Schottky barrier field effect transistors A high-gain MESFET (i.e. a Schottky barrier FET) has a gate electrode present directly on a semiconductor body. A highly doped layer, which forms parts of the channel of the transistor, extends below the gate electrode between the source and drain regions...	12/04/1984
4407004	Self-aligned MESFET having reduced series resistance Disclosed herein is a structure and process for a self-aligned metal semiconductor field effect transistor having the characteristics of a high speed, high density, low power LSI circuit and specifically an improved high device gain MESFET device using co...	09/27/1983
4201997	MESFET semiconductor device and method of making An improved MESFET integrated circuit device with a metal-semiconductor diode as the control element and a source and drain as other device elements is fabricated using a self-aligned gate process which consists of an implanted channel stopper underneath ...	05/06/1980
4202003	MESFET Semiconductor device and method of making A MESFET integrated circuit device with a metal-semiconductor diode as the control element and a source and drain as other device elements is fabricated using a method which consists of an implanted channel stopper underneath a thick field oxide, implante...	05/06/1980
4170818	Barrier height voltage reference A barrier height voltage reference includes two field-effect transistors which are substantially identical except for their gate-to-channel potential barrier characteristics and which are biased to carry equal drain currents at equal drain voltages. The r...	10/16/1979
3946415	Normally off schottky barrier field effect transistor and method of fabrication A normally-off field effect transistor having the structure of an IGFET with a substantially undoped semiconductor material replacing the insulation between the substrate and the gate metal. A Schottky barrier formed between the gate metal and the substan...	03/23/1976

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Class 257/269 - With means to adjust barrier height (e.g., doping profile)