Did You Know...
...that after Parker Brothers executives turned down the game of Monopoly because it had "52 fundamental errors" (including taking too long to play), a copy of the game wound up in the home of the company president who stayed up until 1 a.m. to finish playing it? He was so impressed by the game that the next day he wrote to inventor Charles Darrow and offered to buy it!
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| Number | Title | Issue Date |
| 7700980 | Structure and fabrication of field-effect transistor for alleviating short-channel effects Each of a pair of like-polarity IGFETs (40 or 42 and 240 or 242) has a channel zone (64 or 84) situated in body material (50). Short-channel effects are alleviated by arranging for the net dopant concentration in the ... | 04/20/2010 |
| 7535039 | Vertically integrated dual gate transistor structure and method of making same A dual gate power switch comprised of a vertical arrangement of a normally off SIT (static induction transistor) in series with a normally on SIT in a monolithic semiconductor structure. The structure includes a first pillar having at the base thereof laterally exte... | 05/19/2009 |
| 7439563 | High-breakdown-voltage semiconductor device A high-breakdown-voltage semiconductor device comprises a high-resistance semiconductor layer, trenches formed on the surface thereof in a longitudinal plane shape and in parallel, first regions formed on the semiconductor layer to be sandwiched between adjacent one... | 10/21/2008 |
| 7387936 | Semiconductor device and method of fabricating the same A semiconductor device includes a substrate having a pair of first diffused regions, and a gate including an oxide film provided on the substrate, and a charge storage layer provided on the oxide film, the charge storage layer being an electrical insulator capable o... | 06/17/2008 |
| 7342264 | Memory cell and method for manufacturing the same The invention is directed to a memory cell on a substrate having a plurality of shallow trench isolations form therein, wherein top surfaces of the shallow trench isolations are lower than a top surface of the substrate and the shallow trench isolations together def... | 03/11/2008 |
| 7339206 | Field effect transistor including a group III-V compound semiconductor layer A field effect transistor (FET) includes a first semiconductor layer and a second semiconductor layer, the second semiconductor layer being formed on the first semiconductor layer and having a band gap energy greater than that of the first semiconductor layer. The f... | 03/04/2008 |
| 7288809 | Flash memory with buried bit lines A memory cell and a method of forming the same are described. The memory cell is formed on a substrate. The memory cell includes a floating gate that is formed at least in part within the substrate. A bit line region is formed within the substrate in proximity to th... | 10/30/2007 |
| 7268378 | Structure for reduced gate capacitance in a JFET A junction field effect transistor (JFET) with a reduced gate capacitance. A gate definition spacer is formed on the wall of an etched trench to establish the lateral extent of an implanted gate region for a JFET. After implant, the gate is annealed. In addition to ... | 09/11/2007 |
| 7265398 | Method and structure for composite trench fill A method and structure for a composite trench fill for silicon electronic devices. On a planar silicon substrate having a first deposited layer of oxide and a second deposited layer of polysilicon, a trench is etched. Deposition and etch processes using a combinatio... | 09/04/2007 |
| 7244970 | Low capacitance two-terminal barrier controlled TVS diodes A two-terminal barrier controlled TVS diode has a depletion region barrier blocking majority carrier flow through the channel region at the vicinity of the cathode region at bias levels below the predetermined clamping voltage applied between the anode electrode and... | 07/17/2007 |
| 7230283 | Semiconductor device having a metal conductor in ohmic contact with the gate region on the bottom of each groove A silicon carbide semiconductor device such as JFET, SIT and the like is provided for accomplishing a reduction in on-resistance and high-speed switching operations. In the JFET or SIT which turns on/off a current with a depletion layer extending in a channel betwee... | 06/12/2007 |
| 7221009 | Semiconductor device A dose of arsenic for an extension region in an NMOS transistor is in a range from 5×1014 to 2×1015 ions/cm2 and preferably in a range from 1.1×1015 to 1.5×1015 ions/cm2. Also, in addition to arse... | 05/22/2007 |
| 7211845 | Multiple doped channel in a multiple doped gate junction field effect transistor A multiple doped channel in a multiple doped gate junction field effect transistor. In accordance with a first embodiment of the present invention, a junction field effect transistor (JFET) circuit structure comprises a vertical channel. The vertical channel compris... | 05/01/2007 |
| 7208814 | Resistive device and method for its production A resistive device includes a resistive region of a semiconductor material that includes a first region and a second region, wherein the first region has a higher dopant concentration than the second region, and wherein a resistance-determining width of a current pa... | 04/24/2007 |
| 7187021 | Static induction transistor A transistor switch for a system operating at high frequencies is provided. The transistor switch comprises a graded channel region between a source region and a drain region, the graded channel region configured for providing a low resistance to mobile negative cha... | 03/06/2007 |
| 7169620 | Method of reducing the surface roughness of spin coated polymer films According to one aspect of the invention, a method of constructing a memory array is provided. An insulating layer is formed on a semiconductor wafer. A first metal stack is then formed on the insulating layer and etched to form first metal lines. A polymeric layer ... | 01/30/2007 |
| 7164160 | Integrated circuit device with a vertical JFET We disclose the structure of a JFET device, the method of making the device and the operation of the device. The device is built near the top of a substrate. It has a buried layer that is electrically communicable to a drain terminal. It has a channel region over th... | 01/16/2007 |
| 7164154 | Gate wiring layout for silicon-carbide-based junction field effect transistor A silicon carbide semiconductor device includes: a semiconductor substrate including first and second gate layers, a channel layer, a source layer, and a trench; a gate wiring having a first portion and a plurality of second portions; and a source wiring having a th... | 01/16/2007 |
| 7154177 | Semiconductor device with edge structure A semiconductor device has an edge termination region (15) having a plurality of trenches (17). Conductive material (20) and insulating material (19) is formed at the trenches, and surface implants (21) are formed on either side of... | 12/26/2006 |
| 7074672 | Self aligned method of forming a semiconductor memory array of floating gate memory cells with buried bit-line and vertical word line transistor A self aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate, and an array formed thereby, whereby each memory cell includes a trench formed into a surface of a semiconductor substrate, spaced apart source ... | 07/11/2006 |
| 7038260 | Dual gate structure for a FET and method for fabricating same A method for fabricating a dual gate structure for JFETs and MESFETs and the associated devices. Trenches are etched in a semiconductor substrate for fabrication of a gate structure for a JFET or MESFET. A sidewall spacer may be formed on the walls of the trenches t... | 05/02/2006 |
| 7026668 | High-breakdown-voltage semiconductor device A high-breakdown-voltage semiconductor device comprises a high-resistance semiconductor layer, trenches formed on the surface thereof in a longitudinal plane shape and in parallel, first regions formed on the semiconductor layer to be sandwiched between adjacent one... | 04/11/2006 |
| 6960797 | Semiconductor device The object of the present invention is to provide a semiconductor device, which is suitable for use to connect electric condenser microphones. A semiconductor device, comprises: a conductivity-type substrate; an epitaxial layer formed on top of the substrate; island... | 11/01/2005 |
| 6949401 | Semiconductor component and method for producing the same A method for producing a semiconductor component with adjacent Schottky (5) and pn (9) junctions positions in a drift area (2, 10) of a semiconductor material. According to the method, a silicon carbide substrate doped with a first doping materi... | 09/27/2005 |
| 6946374 | Methods of manufacturing flash memory semiconductor devices A manufacturing method for fabricating flash memory semiconductor devices is disclosed. According to one example, the manufacturing method may include: forming a trench on a silicon substrate by forming a photoresist pattern on the silicon substrate and performing a... | 09/20/2005 |
| 6917069 | Semiconductor memory array of floating gate memory cells with buried bit-line and vertical word line transistor A self aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate, and an array formed thereby, whereby each memory cell includes a trench formed into a surface of a semiconductor substrate, spaced apart source ... | 07/12/2005 |
| 6894346 | Semiconductor device A structure is provided that ensures a low on-resistance and a better blocking effect. In a lateral type SIT (Static Induction Transistor) in which a first region is used as a p+ gate and a gate electrode is formed on the bottom of the first region, the s... | 05/17/2005 |
| 6870189 | Pinch-off type vertical junction field effect transistor and method of manufacturing the same A junction field effect transistor (JFET) is provided that is capable of a high voltage resistance, high current switching operation, that operates with a low loss, and that has little variation. This JFET is provided with a gate region (2) of a second conduc... | 03/22/2005 |
| 6855970 | High-breakdown-voltage semiconductor device A high-breakdown-voltage semiconductor device comprises a high-resistance semiconductor layer, trenches formed on the surface thereof in a longitudinal plane shape and in parallel, first regions formed on the semiconductor layer to be sandwiched between adjacent one... | 02/15/2005 |
| 6774408 | Trench gate power device having a concentration at channel layer higher than a base layer and uniformly distributed along the depth of the trench and its manufacturing method In a trench MOS gate structure of a semiconductor device where trenches (T) are located between an n-type base layer (1) and an n-type source layer (3), a p-type channel layer (12) is formed adjacent to side walls of the trenches, having an even... | 08/10/2004 |
| 6750477 | Static induction transistor In a static induction transistor, in addition to a first gate layer (4), a plurality of second gate layers (41) having a shallower depth and a narrower gap therebetween than those of the first gate layer (4) are provided in an area surrounded by... | 06/15/2004 |
| 6693300 | Semiconductor thin film and semiconductor device A semiconductor thin film having extremely superior crystallinity and a semiconductor device using the semiconductor thin film having high performance are provided. The semiconductor thin film is manufactured in such a manner that after an amorphous semic... | 02/17/2004 |
| 6674107 | Enhancement mode junction field effect transistor with low on resistance A normally "off" enhancement mode junction field effect transistor (JFET) is disclose. The JFET has a low threshold voltage in the range of 0.2 to 0.3 volts and a low on resistance. The Drain-to-Source voltage drop is less than 0.1 volt at a drain current... | 01/06/2004 |
| 6555857 | Semiconductor device The object of the present invention is to provide a semiconductor device, which is suitable for use to connect electric condenser microphones. A semiconductor device, comprises: a conductivity-type substrate; an epitaxial layer formed on top of the substr... | 04/29/2003 |
| 6396084 | Structure of semiconductor rectifier A semiconductor rectifier includes a substrate of a first conductivity type; a current path layer of the first conductivity type formed near the surface of the substrate; a current block layer of a second conductivity type laterally enclosing the current ... | 05/28/2002 |
| 6307223 | Complementary junction field effect transistors Junction Field Effect Transistor (JFET) offers fast switching speed than bipolar transistor since JFET is a majority carrier device. This invention comprises two normally "off" JFETs, one in N-channel and one in P-channel to form Complementary Junction Fi... | 10/23/2001 |
| 6069371 | Semiconductor rectifier and a method for driving the same A semiconductor rectifier in which the sum of loss during reverse recovery and loss in a conducting state can be suppressed even if the ratio between the periods of the conducting and blocking states varies and a method of driving the same are disclosed. ... | 05/30/2000 |
| 5962893 | Schottky tunneling device An n-semiconductor layer is arranged on a low-resistance n-substrate. A drain electrode is in ohmic contact with the n-substrate. A source electrode forms a Schottky junction with the n-semiconductor layer. A gate electrode is arranged adjacent to the sou... | 10/05/1999 |
| 5945701 | Static induction transistor A static induction transistor having source, drain and gate regions. Channel regions are defined between adjacent gates and a drift region is defined from the ends of the channel regions to the drain. The channel and drift regions have predetermined dopin... | 08/31/1999 |
| 5903020 | Silicon carbide static induction transistor structure A static induction transistor having a silicon carbide substrate upon which is deposited a silicon carbide layer arrangement. The layer arrangement has a plurality of spaced gate regions for controlling current flow from a source region to a drain region ... | 05/11/1999 |
