Did You Know...
...that a workman who left the soap mixing machine on too long was responsible for making Ivory Soap? He was so embarrassed by his mistake that he threw the mess in a stream. Imagine his dismay when the evidence of his error floated to the surface! Result: Ivory soap, the soap that floats.
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| Number | Title | Issue Date |
| 8183605 | Reducing transistor junction capacitance by recessing drain and source regions By recessing portions of the drain and source areas on the basis of a spacer structure, the subsequent implantation process for forming the deep drain and source regions may result in a moderately high dopant concentration extending down to the buried insulating lay... | 05/22/2012 |
| 8174057 | CMOS image device with local impurity region According to a CMOS image device and a method of manufacturing same, dark current is decreased by a local impurity region. The image device includes a semiconductor substrate, and a transfer gate formed on a predetermined portion of the semiconductor substrate and e... | 05/08/2012 |
| 8154059 | Semiconductor device and method for manufacturing the same An object of the present invention is to prevent the deterioration of a TFT (thin film transistor). The deterioration of the TFT by a BT test is prevented by forming a silicon oxide nitride film between the semiconductor layer of the TFT and a substrate, wherein the... | 04/10/2012 |
| 8120071 | MEMFET RAM A non-volatile field-effect device. The non-volatile field-effect device includes a source, a drain, a channel-formation portion and a memristive gate. The channel-formation portion is disposed between and coupled with the source and the drain. The memristive gate i... | 02/21/2012 |
| 8072011 | Semiconductor device and method for operating the same A semiconductor device includes a lateral double diffused metal oxide semiconductor (LDMOS) , a junction field effect transistor (JFET) and an inner circuit. The lateral double diffused metal oxide semiconductor includes a first source, a common drain and a first ga... | 12/06/2011 |
| 7956390 | Semiconductor device and manufacturing method thereof A semiconductor device having a semiconductor substrate, a first impurity region including a first conductive impurity formed in the semiconductor substrate, a first transistor and a second transistor formed in the first impurity region, a first stress film and a se... | 06/07/2011 |
| 7939863 | Area efficient 3D integration of low noise JFET and MOS in linear bipolar CMOS process Analog ICs frequently include circuits which operate over a wide current range. At low currents, low noise is important, while IC space efficiency is important at high currents. A vertically integrated transistor made of a JFET in parallel with an MOS transistor, sh... | 05/10/2011 |
| 7768042 | Thin film transistor including titanium oxides as active layer and method of manufacturing the same Disclosed herein is a method of manufacturing a thin film transistor including titanium oxides as an active layer and the structure of the thin film transistor film manufactured using the method. The thin film transistor includes: a substrate; an active layer formed... | 08/03/2010 |
| 7692221 | Semiconductor device having IGBT element A semiconductor device having an insulated gate bipolar transistor (IGBT) is formed on a semiconductor substrate. A base region and an emitter are formed on a first surface of the substrate while a collector layer is formed on second surface of the substrate. A regi... | 04/06/2010 |
| 7453106 | Semiconductor device with stress reducing trench fill containing semiconductor microparticles in shallow trench isolation A semiconductor device includes: a semiconductor substrate formed with an active region and an isolation region and having a trench formed in the isolation region; an isolation insulating film embedded in the trench of the semiconductor substrate; and semiconductor ... | 11/18/2008 |
| 7381603 | Semiconductor structure with improved on resistance and breakdown voltage performance In one embodiment, a lateral FET cell is formed in a body of semiconductor material. The lateral FET cell includes a super junction structure formed in a drift region between a drain contact and a body region. The super junction structure includes a plurality of spa... | 06/03/2008 |
| 7368777 | Accumulation device with charge balance structure and method of forming the same An accumulation-mode field effect transistor includes a plurality of gates and a semiconductor region having a channel region adjacent to but insulated from each of the plurality of gates. The semiconductor region further includes a conduction region wherein the cha... | 05/06/2008 |
| 7365402 | LDMOS transistor An LDMOS semiconductor transistor structure comprises a substrate having an epitaxial layer of a first conductivity type, a source region extending from a surface of the epitaxial layer of a second conductivity type, a lightly doped drain region within the epitaxial... | 04/29/2008 |
| 7355224 | High voltage LDMOS A semiconductor device, such as a LDMOS device, comprising: a semiconductor substrate; a drain region in the semiconductor substrate; a source region in the semiconductor substrate laterally spaced from the drain region; and a drift region in the semiconductor subst... | 04/08/2008 |
| 7352018 | Non-volatile memory cells and methods for fabricating non-volatile memory cells The invention relates to a method for fabricating stacked non-volatile memory cells. Further, the invention relates to stacked non-volatile memory cells. The invention particularly relates to the field of non-volatile NAND memories having non-volatile stacked memory... | 04/01/2008 |
| 7342265 | Vertical-type semiconductor device having repetitive-pattern layer A semiconductor device is fabricated to include a withstand-voltage assurance layer designed into a multi-dimensional super junction structure and a group of trench gate electrodes, each of which penetrating a body layer in contact with the multi-dimensional super j... | 03/11/2008 |
| 7339213 | Semiconductor device having a triple gate transistor and method for manufacturing the same In a semiconductor capable of reducing NBTI and a method for manufacturing the same, a multi-gate transistor includes an active region, gate dielectric, channels in the active region, and gate electrodes, and is formed on a semiconductor wafer. The active region has... | 03/04/2008 |
| 7335952 | Semiconductor device and manufacturing method therefor To provide a semiconductor device that permits free setting of characteristics of individual semiconductor elements which are mixedly mounted and have different characteristics, and is free of steps between formed semiconductor elements, in a manufacturing method fo... | 02/26/2008 |
| 7323716 | Manufacturing method of thin film transistor substrate This invention provides a manufacturing method for fabricating on the same substrate both high voltage thin film transistors suitable for driving liquid crystal and low voltage drive high performance thin film transistors. In addition, this invention provides a thin... | 01/29/2008 |
| 7253492 | Semiconductor structure with via structure A semiconductor device may comprise a semiconductor substrate having a top and a bottom surface, first and second insulating layer deposited on the top surface of the substrate, a runner arranged on top of the second insulator layer, a backside metal layer deposited... | 08/07/2007 |
| 7239007 | Bipolar transistor with divided base and emitter regions A modified bipolar transistor defined for providing a larger emitter current than a basic emitter current from a basic bipolar transistor is provided. The modified transistor has an improved emitter structure comprising plural divided sub-emitter regions electricall... | 07/03/2007 |
| 7237258 | System, method and computer program product for a firewall summary interface A system, method and computer program product are provided for summarizing firewall activity. Initially, a plurality of types of events associated with a firewall of a local computer is organized. Further, a number of occurrences of each type of event is tracked uti... | 06/26/2007 |
| 7235860 | Bipolar transistor including divided emitter structure A modified bipolar transistor defined for providing a larger emitter current than a basic emitter current from a basic bipolar transistor is provided. The modified transistor has an improved emitter structure comprising plural divided sub-emitter regions electricall... | 06/26/2007 |
| 7227203 | Power system inhibit method and device and structure therefor A power control system (25) uses two separate currents to control a startup operation of the power control system (25). The two currents are shunted to ground to inhibit operation of the power control system (25) and one of the two currents is d... | 06/05/2007 |
| 7221034 | Semiconductor structure including vias A semiconductor device may comprise a semiconductor substrate having a top and a bottom surface, first and second insulating layer deposited on the top surface of the substrate, a runner arranged on top of the second insulator layer, a backside metal layer deposited... | 05/22/2007 |
| 7202517 | Multiple gate semiconductor device and method for forming same A multiple gate semiconductor device. The device includes at least two gates. The dopant distribution in the semiconductor body of the device varies from a low value near the surface of the body towards a higher value inside the body of the device. ... | 04/10/2007 |
| 7186630 | Deposition of amorphous silicon-containing films Chemical vapor deposition methods are used to deposit amorphous silicon-containing films over various substrates. Such methods are useful in semiconductor manufacturing to provide a variety of advantages, including uniform deposition over heterogeneous surfaces, hig... | 03/06/2007 |
| 7183662 | Memory devices with memory cell transistors having gate sidewell spacers with different dielectric properties A memory device, such as a DRAM, SRAM or non-volatile memory device, includes a substrate, a gate electrode disposed on the substrate, and source and drain regions in the substrate adjacent respective first and second sidewalls of the gate electrode. First and secon... | 02/27/2007 |
| 7180106 | Semiconductor device having enhanced di/dt tolerance and dV/dt tolerance A semiconductor device has an enhanced di/dt tolerance and a dv/dt tolerance without increasing an ON resistance. An underpad base region is provided on a region in an upper main surface of a semiconductor substrate which is provided under a gate pad, and the underp... | 02/20/2007 |
| 7180134 | Methods and structures for planar and multiple-gate transistors formed on SOI A semiconductor device includes an insulator layer, a semiconductor layer, a first transistor, and a second transistor. The semiconductor layer is overlying the insulator layer. A first portion of the semiconductor layer has a first thickness. A second portion of th... | 02/20/2007 |
| 7169655 | Field effect transistors and methods for manufacturing field effect transistors FETs and methods for fabricating FETs are disclosed. An illustrated method comprises forming a first insulating layer on a semiconductor substrate; forming a first conductive layer for a fin on the first insulating layer; etching the first conductive layer so that a... | 01/30/2007 |
| 7161210 | Semiconductor device with source and drain regions A semiconductor device is provided with a gate electrode formed over a substrate that has gate oxide films disposed thereon. Source-drain regions of low and high concentration are formed next to the gate electrode. A diffusion region width of the source side of the ... | 01/09/2007 |
| 7160780 | Method of manufacturing a fin field effect transistor In an exemplary embodiment, a fin active region is protruded along one direction from a bulk silicon substrate on which a shallow trench insulator is entirely formed so as to cover the fin active region. The shallow trench insulator is removed to selectively expose ... | 01/09/2007 |
| 7141856 | Multi-structured Si-fin Disclosed is a semiconductor fin construction useful in FinFET devices that incorporates an upper region and a lower region with wherein the upper region is formed with substantially vertical sidewalls and the lower region is formed with inclined sidewalls to produc... | 11/28/2006 |
| 7135368 | Semiconductor memory device with surface strap and method of fabricating the same A method of fabricating a semiconductor memory device, comprising recess-etching a major surface of a semiconductor substrate, thereby forming a pillar that becomes a device formation region; burying an insulation film in the recess-etched region, thereby forming a ... | 11/14/2006 |
| 7125777 | Asymmetric hetero-doped high-voltage MOSFET (AHMOS) An asymmetric hetero-doped metal oxide (AH2MOS) semiconductor device includes a substrate and an insulated gate on the top of the substrate disposed between a source region and a drain region. On one side of the gate, heterodoped tub and source regions ar... | 10/24/2006 |
| 7119399 | LDMOS transistor A semiconductor device has a semiconductor substrate, an insulating layer on top of the substrate, a lateral field effect transistor with a drain region and a source region arranged in the substrate and a gate arranged above the substrate within the insulating layer... | 10/10/2006 |
| 7112828 | Semiconductor device A semiconductor device that permits an increase in static destruction resistance while preventing an increase in the chip size includes a protective element formed by a polysilicon layer in which JFETs are serially connected in three stages and which is inserted bet... | 09/26/2006 |
| 7109562 | High voltage laterally double-diffused metal oxide semiconductor A high voltage laterally double-diffused metal oxide semiconductor (LDMOS) stricture is characterized as follows: the second source electrode metal layer connected to the first source electrode metal layer protrudes out of a certain length relative to the first sour... | 09/19/2006 |
| 7095065 | Varying carrier mobility in semiconductor devices to achieve overall design goals A semiconductor device may include a substrate and an insulating layer formed on the substrate. A first device may be formed on the insulating layer, including a first fin. The first fin may be formed on the insulating layer and may have a first fin aspect ratio. A ... | 08/22/2006 |
