Famous Patents
The first commercial microwave oven was nearly 6 feet tall and weighed in at 750 pounds.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 7982249 | Magnetic tunnel junction transistor A magnetic tunnel junction transistor. In a particular embodiment, the magnetic tunnel junction transistor includes a tunnel barrier having a high resistance when in a non-ferromagnetic, state and a low resistance when in a ferromagnetic state. The tunnel barrier is... | 07/19/2011 |
| 7821045 | Apparatus, system, and method for multiple-segment floating gate Various embodiments include a substrate and a memory cell coupled to the substrate. The memory cell may include an L-shaped floating gate, a control gate, an insulation layer coupled between the control gate and the first L-shaped floating gate, and a conductive lay... | 10/26/2010 |
| 7557393 | JFET with built in back gate in either SOI or bulk silicon A Junction Field-Effect transistor with no surface contact for the back gate and twice as much transconductance in the channel and with a higher switching speed is achieved by intentionally shorting the channel-well PN junction with the gate region. This is achieved... | 07/07/2009 |
| 7528425 | Semiconductor memory with charge-trapping stack arrangement A semiconductor memory having a multitude of memory cells (21-1), the semiconductor memory having a substrate (1), at least one wordline (5-1), a first (15-1) and a second line (15-2; 16-1), where... | 05/05/2009 |
| 7439563 | High-breakdown-voltage semiconductor device A high-breakdown-voltage semiconductor device comprises a high-resistance semiconductor layer, trenches formed on the surface thereof in a longitudinal plane shape and in parallel, first regions formed on the semiconductor layer to be sandwiched between adjacent one... | 10/21/2008 |
| 7439567 | Contactless nonvolatile memory array An array of memory cells with non-volatile memory transistors having a compact arrangement of diagonally symmetric floating gates. The floating gates have portions extending in both X and Y directions, allowing them to be charged through a common tunnel oxide stripe... | 10/21/2008 |
| 7402850 | Back-side trapped non-volatile memory device Non-volatile memory devices and arrays are described that utilize back-side trapped floating node memory cells with band-gap engineered gate stacks with asymmetric tunnel barriers. Embodiments of the present invention allow for direct tunneling programming and effic... | 07/22/2008 |
| 7388240 | Non-volatile memory device capable of preventing damage by plasma charge A non-volatile memory device for preventing damage by plasma charges includes a gate electrode formed on a predetermined region of a semiconductor substrate, a source/drain region which is overlapped with the gate electrode and formed in a first well region of the s... | 06/17/2008 |
| 7348239 | Semiconductor device and method of manufacturing the same A semiconductor device and a method of manufacturing the same, wherein first and second gate electrodes are formed to have a spacer shape. The length of an underlying dielectric film can be automatically controlled. A gate oxide film and a third gate electrode are f... | 03/25/2008 |
| 7345296 | Nanotube transistor and rectifying devices Single-walled carbon nanotube transistor and rectifying devices, and associated methods of making such devices include a porous structure for the single-walled carbon nanotubes. The porous structure may be anodized aluminum oxide or another material. Electrodes for ... | 03/18/2008 |
| 7315068 | Interface layer for the fabrication of electronic devices The present invention is directed to methods for making electronic devices with a thin anisotropic conducting layer interface layer formed between a substrate and an active device layer that is preferably patterned conductive layer. The interface layer preferably pr... | 01/01/2008 |
| 7301197 | Non-volatile nanocrystal memory transistors using low voltage impact ionization A low voltage non-volatile charge storage transistor has a nanocrystal layer for permanently storing charge until erased. A subsurface charge injector generates secondary carriers by stimulating electron-hole current flowing toward the substrate, with some carriers ... | 11/27/2007 |
| 7262457 | Non-volatile memory cell A memory cell includes an N-type well, three P-type doped regions, a first stacked dielectric layer, a first gate, a second stacked dielectric layer, and a second gate. The three P-type doped regions are formed on the N-well. The first dielectric stack layer is form... | 08/28/2007 |
| 7259101 | Nanoparticles and method for making the same A method for making nanoparticles, nanoparticle inks and device layers therefrom is disclosed. In accordance with the present invention, nanoparticles are isolated from a composite material that is formed by treating a metal oxide precursor to form the metal nanopar... | 08/21/2007 |
| 7259100 | Nanoparticles and method for making the same A method for making nanoparticles, nanoparticle inks and device layers therefrom is disclosed. In accordance with the present invention, nanoparticles are isolated from a composite material that is formed by treating a metal oxide precursor to form the metal nanopar... | 08/21/2007 |
| 7239554 | Nonvolatile memory device and method of improving programming characteristic A method of programming a non-volatile memory device includes activating a first pump to generate a bitline voltage, and after the bulk voltage reaches a target voltage, detecting whether the bitline voltage is less than a detection voltage. When the bitline voltage... | 07/03/2007 |
| 7221008 | Bitline direction shielding to avoid cross coupling between adjacent cells for NAND flash memory A NAND flash memory structure and method of making a flash memory structure with shielding in the bitline direction as well as in wordline and diagonal directions from Yupin effect errors and from disturbs. ... | 05/22/2007 |
| 7221017 | Memory utilizing oxide-conductor nanolaminates Structures, systems and methods for floating gate transistors utilizing oxide-conductor nanolaminates are provided. One floating gate transistor embodiment includes a first source/drain region, a second source/drain region, and a channel region therebetween. A float... | 05/22/2007 |
| 7221586 | Memory utilizing oxide nanolaminates Structures, systems and methods for transistors utilizing oxide nanolaminates are provided. One transistor embodiment includes a first source/drain region, a second source/drain region, and a channel region therebetween. A gate is separated from the channel region b... | 05/22/2007 |
| 7208796 | Split gate flash memory A split gate flash memory is provided. Trenches are formed in the substrate to define active layers. The device isolation layers are formed in the trenches. The surface of the device isolation layers is lower than the surface of the active layers. The stacked gate s... | 04/24/2007 |
| 7193893 | Write once read only memory employing floating gates Structures and methods for write once read only memory employing floating gates are provided. The write once read only memory cell includes a floating gate transistor formed in a modified dynamic random access memory (DRAM) fabrication process. The floating gate tra... | 03/20/2007 |
| 7166509 | Write once read only memory with large work function floating gates Structures and methods for write once read only memory employing floating gates are provided. The write once read only memory cell includes a floating gate transistor formed in a modified dynamic random access memory (DRAM) fabrication process. The floating gate tra... | 01/23/2007 |
| 7154140 | Write once read only memory with large work function floating gates Structures and methods for write once read only memory employing floating gates are provided. The write once read only memory cell includes a floating gate transistor formed in a modified dynamic random access memory (DRAM) fabrication process. The floating gate tra... | 12/26/2006 |
| 7129562 | Dual-height cell with variable width power rail architecture A standard cell architecture with a basic cell that spans multiple rows of the standard cell. This multi-row basic cell may be a dual-height cell that spans two rows, or it may span more than two rows. The multi-row basic cell may be intermixed in a standard cell de... | 10/31/2006 |
| 7121474 | Electro-optical nanocrystal memory device A memory device. The memory device includes a substrate and an array of nanocrystals formed proximate to the substrate. The array of nanocrystals is electrically insulated to hold charge carriers therein. A presence of charge carriers within the array of nanocrystal... | 10/17/2006 |
| 7112494 | Write once read only memory employing charge trapping in insulators Structures and methods for write once read only memory employing charge trapping in insulators are provided. The write once read only memory cell includes a metal oxide semiconductor field effect transistor having a first source/drain region, a second source/drain r... | 09/26/2006 |
| 7105884 | Memory circuitry with plurality of capacitors received within an insulative layer well A method of forming memory circuitry having a memory array having a plurality of memory capacitors and having peripheral memory circuitry operatively configured to write to and read from the memory array, includes forming a dielectric well forming layer over a semic... | 09/12/2006 |
| 7098505 | Memory device with multiple memory layers of local charge storage A multiple memory layer device has a plurality of stacked memory layers. Each of the memory layers has: a charge generating layer of p-type semiconductor material with a plurality of n-type diffusion regions; an insulating layer disposed over the charge generating l... | 08/29/2006 |
| 7078276 | Nanoparticles and method for making the same A method for making nanoparticles, nanoparticle inks and device layers therefrom is disclosed. In accordance with the present invention, nanoparticles are isolated from a composite material that is formed by treating a metal oxide precursor to form the metal nanopar... | 07/18/2006 |
| 7053463 | High-voltage integrated vertical resistor and manufacturing process thereof The manufacturing process comprises the steps of growing epitaxially a first layer from a semiconductor material substrate, forming in the first layer a first and a second buried region spaced from one another and having conductivity of the type opposite that of the... | 05/30/2006 |
| 7045851 | Nonvolatile memory device using semiconductor nanocrystals and method of forming same A floating gate for a field effect transistor (and method for forming the same and method of forming a uniform nanoparticle array), includes a plurality of discrete nanoparticles in which at least one of a size, spacing, and density of the nanoparticles is one of te... | 05/16/2006 |
| 7018898 | Non-volatile two transistor semiconductor memory cell and method for producing the same The invention relates to a nonvolatile two-transistor semiconductor memory cell and an associated fabrication method, source and drain regions (2) for a selection transistor (AT) and a memory transistor (ST) being formed in a substrate (1). The memory ... | 03/28/2006 |
| 7015546 | Deterministically doped field-effect devices and methods of making same Deterministically doped field-effect devices and methods of making same. One or more dopant atoms, also referred to as impurities or impurity atoms, are arranged in the channel region of a device in engineered arrays. Component atoms of an engineered array are subst... | 03/21/2006 |
| 6996009 | NOR flash memory cell with high storage density Structures and methods for NOR flash memory cells, arrays and systems are provided. The NOR flash memory cell includes a vertical floating gate transistor extending outwardly from a substrate. The floating gate transistor having a first source/drain region, a second... | 02/07/2006 |
| 6979860 | Semiconductor device and manufacturing method thereof A plurality of first wiring structures of a first width are arranged periodically at first intervals. A second wiring structure is formed next to one of the first wiring structures. The lower part of the second wiring structure has a second width substantially equal... | 12/27/2005 |
| 6970370 | Ferroelectric write once read only memory for archival storage Structures and methods for ferroelectric write once read only memory adapted to be programmed for long retention archival storage are provided. The write once read only memory cell includes a charge amplifier transistor. The transistor includes a source region, a dr... | 11/29/2005 |
| 6965142 | Floating-gate semiconductor structures Hot-electron injection driven by hole impact ionization in the channel-to-drain junction of a p-channel MOSFET provides a new mechanism for writing a floating-gate memory. Various pFET floating-gate structures use a combination of this mechanism and electron tunneli... | 11/15/2005 |
| 6958510 | Process for fabricating a dual charge storage location memory cell A process for fabricating a dual charge storage location, electrically programmable memory cell, comprising: forming a first dielectric layer over a semiconductor material layer of a first conductivity type; forming a charge trapping material layer over the first di... | 10/25/2005 |
| 6952362 | Ferroelectric write once read only memory for archival storage Structures and methods for ferroelectric write once read only memory adapted to be programmed for long retention archival storage are provided. The write once read only memory cell includes a charge amplifier transistor. The transistor includes a source region, a dr... | 10/04/2005 |
| 6936883 | Bi-directional read/program non-volatile floating gate memory cell and array thereof, and method of formation A bi-directional read/program non-volatile memory cell and array is capable of achieving high density. Each memory cell has two spaced floating gates for storage of charges thereon. The cell has spaced apart source/drain regions with a channel therebetween, with the... | 08/30/2005 |
