Class 257/260 - Same channel controlled by both junction and insulated gate electrodes, or by both Schottky barrier and pn junction gates (e.g., "taper isolated" memory cell)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: Subject matter including plural gate electrodes or regions,
No. of patents: 114
Last issue date: 04/03/2012

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Number	Title	Issue Date
8148758	High voltage semiconductor device with JFET regions containing dielectrically isolated junctions and method of fabricating the same A high-voltage field-effect device contains an extended drain or “drift” region including an embedded stack of JFET regions separated by intervening layers of the drift region. Each of the JFET regions is filled with material of an opposite conductivity type to ...	04/03/2012
8143653	Variable resistance memory device and system thereof A phase-change random access memory device is provided. The phase-change random access memory device includes a global bit line connected to a write circuit and a read circuit, multiple local bit lines, each being connected to multiple phase-change memory cells, and...	03/27/2012
7910962	SOI trench lateral IGBT To enable driving at a high withstand voltage and a large current, increase latchup immunity, and reduce ON resistance per unit area in an IGBT, a trench constituted by an upper stage trench and a lower stage trench is formed over an entire wafer surface between an ...	03/22/2011
7888711	Continuous plane of thin-film materials for a two-terminal cross-point memory A structure for a memory device including a plurality of substantially planar thin-film layers or a plurality of conformal thin-film layers is disclosed. The thin-film layers form a memory element that is electrically in series with first and second cladded conducto...	02/15/2011
7696540	Structure and method for a fast recovery rectifier structure An apparatus and method for a fast recovery rectifier structure. Specifically, the structure includes a substrate of a first dopant. A first epitaxial layer lightly doped with the first dopant is coupled to the substrate. A first metallization layer is coupled to th...	04/13/2010
7649217	Thin film field effect transistors having Schottky gate-channel junctions An active electronic device has drain and source electrodes that make ohmic conduct with a layer of a semiconductor. The semiconductor layer may be a thin layer of an organic or amorphous semiconductor. The drain and source electrodes are on a first face of the laye...	01/19/2010
7629631	High voltage semiconductor devices with JFET regions containing dielectrically isolated junctions A high-voltage field-effect device contains an extended drain or “drift” region having a plurality of JFET regions separated by portions of the drift region. Each of the JFET regions is filled with material of an opposite conductivity type to that of the drift r...	12/08/2009
7629632	Insulated-gate field effect transistor In a heterostructure field effect transistor (MISHFET), a source ohmic electrode 105 and a drain ohmic electrode 106 are formed on an AlGaN barrier layer 104. A SiNx gate insulator 108, a p-type polycrystalline SiC layer 109, and a...	12/08/2009
7354825	Methods and apparatus to form gates in semiconductor devices A method of formation a gate in a semiconductor device includes forming a gate oxide layer and a sacrificial layer on a semiconductor substrate. The sacrificial layer is then selectively etched to form a sidewall opening. Next, a polycrystalline silicon layer is for...	04/08/2008
7355224	High voltage LDMOS A semiconductor device, such as a LDMOS device, comprising: a semiconductor substrate; a drain region in the semiconductor substrate; a source region in the semiconductor substrate laterally spaced from the drain region; and a drift region in the semiconductor subst...	04/08/2008
7349273	Access circuit and method for allowing external test voltage to be applied to isolated wells An access circuit selectively couples an externally accessible terminal to each of a plurality of isolated DRAM wells in which respective DRAM arrays are fabricated. The access circuit for each well includes first and second transistors fabricated in respective well...	03/25/2008
7339206	Field effect transistor including a group III-V compound semiconductor layer A field effect transistor (FET) includes a first semiconductor layer and a second semiconductor layer, the second semiconductor layer being formed on the first semiconductor layer and having a band gap energy greater than that of the first semiconductor layer. The f...	03/04/2008
7327002	Industrial control circuit using a single-chip microprocessor An industrial control circuit includes: a first isolation circuit (22) for converting an analog signal to a low level voltage; a single-chip microprocessor SCM (23) for receiving the low level voltage from the first isolation circuit, and generating a ...	02/05/2008
7312481	Reliable high-voltage junction field effect transistor and method of manufacture therefor The present invention provides a high-voltage junction field effect transistor (JFET), a method of manufacture and an integrated circuit including the same. One embodiment of the high-voltage junction field effect transistor (JFET) (300) includes a well regio...	12/25/2007
7310259	Access circuit and method for allowing external test voltage to be applied to isolated wells An access circuit selectively couples an externally accessible terminal to each of a plurality of isolated DRAM wells in which respective DRAM arrays are fabricated. The access circuit for each well includes first and second transistors fabricated in respective well...	12/18/2007
7268378	Structure for reduced gate capacitance in a JFET A junction field effect transistor (JFET) with a reduced gate capacitance. A gate definition spacer is formed on the wall of an etched trench to establish the lateral extent of an implanted gate region for a JFET. After implant, the gate is annealed. In addition to ...	09/11/2007
7265398	Method and structure for composite trench fill A method and structure for a composite trench fill for silicon electronic devices. On a planar silicon substrate having a first deposited layer of oxide and a second deposited layer of polysilicon, a trench is etched. Deposition and etch processes using a combinatio...	09/04/2007
7253031	Semiconductor device and manufacturing method thereof A pin diode is formed by a p+ collector region, an n type buffer region, an n− region and an n+ cathode region. A trench is formed from the surface of n+ cathode region through n+ cathode region to reach n	08/07/2007
7250343	Power transistor arrangement and method for fabricating it In the case of the cost-effective method according to the invention for fabricating a power transistor arrangement, a trench power transistor arrangement (1) is fabricated with four patterning planes each containing a lithography step. The power transistor ar...	07/31/2007
7250666	Schottky barrier diode and method of forming a Schottky barrier diode Disclosed is a silicon-on-insulator-based Schottky barrier diode with a low forward voltage that can be manufactured according to standard SOI process flow. An active silicon island is formed using an SOI wafer. One area of the island is heavily-doped with an n-type...	07/31/2007
7238976	Schottky barrier rectifier and method of manufacturing the same A Schottky barrier rectifier, in accordance with embodiments of the present invention, includes a first conductive layer and a semiconductor. The semiconductor includes a first doped region, a second doped region and a plurality of third doped regions. The second do...	07/03/2007
7208785	Self-aligned Schottky-barrier clamped planar DMOS transistor structure and its manufacturing methods The self-aligned Schottky-barrier clamped planar DMOS transistor structure comprises a self-aligned source region being surrounded by a planar gate region. The self-aligned source region comprises a moderately-doped p-base diffusion ring being formed in a lightly-do...	04/24/2007
7199442	Schottky diode structure to reduce capacitance and switching losses and method of making same A SiC Schottky barrier diode (SBD) is provided having a substrate and two or more epitaxial layers, including at least a thin, lightly doped N-type top epitaxial layer, and an N-type epitaxial layer on which the topmost epitaxial layer is disposed. Multiple epitaxia...	04/03/2007
7186615	Method of forming a floating gate for a split-gate flash memory device A new method to form a floating gate for a flash memory device is achieved. The method comprises forming a gate dielectric layer overlying a substrate. A first conductor layer is deposited overlying the gate dielectric layer. A masking layer is formed overlying the ...	03/06/2007
7156717	situ finishing aid control A method of using finishing aids for advanced finishing control is described. A finishing surface is used generally to induce frictional wear. The finishing aids with preferred in situ control can improve control of the coefficient of friction, the tangential force ...	01/02/2007
7129547	Method of fabricating a high performance MOSFET device featuring formation of an elevated source/drain region A method of fabricating a MOSFET device featuring a raised source/drain structure on a heavily doped source/drain region as well as on a portion of a lightly doped source/drain (LDD), region, after removal of an insulator spacer component, has been developed. After ...	10/31/2006
7122857	Multi-level (4state/2-bit) stacked gate flash memory cell A method is provided for forming a highly dense stacked gate flash memory cell with a structure having multi floating gates that can assume 4 states and, therefore, store 2 bits at the same time. This is accomplished by providing a semiconductor substrate having gat...	10/17/2006
7116570	Access circuit and method for allowing external test voltage to be applied to isolated wells An access circuit selectively couples an externally accessible terminal to each of a plurality of isolated DRAM wells in which respective DRAM arrays are fabricated. The access circuit for each well includes first and second transistors fabricated in respective well...	10/03/2006
7105884	Memory circuitry with plurality of capacitors received within an insulative layer well A method of forming memory circuitry having a memory array having a plurality of memory capacitors and having peripheral memory circuitry operatively configured to write to and read from the memory array, includes forming a dielectric well forming layer over a semic...	09/12/2006
7102207	Semiconductor device having rectifying action A semiconductor device including a base layer of a first conductivity type having a first main surface and a second main surface opposite the first main surface, a first main electrode layer connected to the first main surface, control regions arranged inside groove...	09/05/2006
7098521	Reduced guard ring in schottky barrier diode structure Schottky barrier diodes use a dielectric separation region to bound an active region. The dielectric separation region permits the elimination of a guard ring in at least one dimension. Further, using a dielectric separation region in an active portion of the integr...	08/29/2006
7091533	Semiconductor component The invention relates to a semiconductor component, in which regions of the conduction type opposite to the conduction type of the drift zone are incorporated in the drift zone and also in the region of the active zones. ...	08/15/2006
7087472	Method of making a vertical compound semiconductor field effect transistor device In one embodiment, a method for fabricating a compound semiconductor vertical FET device includes forming a first trench in a body of semiconductor material, and forming a self-aligned second trench within the first trench to define a channel region. A doped gate re...	08/08/2006
7087983	Manufacturing methods of semiconductor devices and a solid state image pickup device A manufacturing method of manufacturing a semiconductor device having a plurality of wiring layers. The method includes the steps of forming a wiring by a first wiring layer as a pattern by dividing a desired pattern into a plurality of patterns, connecting the divi...	08/08/2006
7084457	DMOS device having a trenched bus structure A DMOS device having a trench bus structure thereof is introduced. The trench bus structure comprises a field oxide layer formed on a P substrate, and a trench extending from an top surface of the field oxide layer down to a lower portion of the P substrate. A gate ...	08/01/2006
7078296	Self-aligned trench MOSFETs and methods for making the same Self-aligned trench MOSFETs and methods for manufacturing the same are disclosed. By having a self-aligned structure, the number of MOSFETS per unit area—the cell density—is increased, making the MOSFETs cheaper to produce. The self-aligned structure for the MOS...	07/18/2006
7075132	Programmable junction field effect transistor and method for programming the same A programmable junction field effect transistor (JFET) with multiple independent gate inputs. A drain, source and a plurality of gate regions for controlling a conductive channel between the source and drain are fabricated in a semiconductor substrate. A first porti...	07/11/2006
7042245	Low power consumption MIS semiconductor device A logic gate is constructed of an insulated gate field effect transistor (MIS transistor) having a thin gate insulation film. An operation power supply line to the logic gate is provided with an MIS transistor having a thick gate insulation film for switching the su...	05/09/2006
7027316	Access circuit and method for allowing external test voltage to be applied to isolated wells An access circuit selectively couples an externally accessible terminal to each of a plurality of isolated DRAM wells in which respective DRAM arrays are fabricated. The access circuit for each well includes first and second transistors fabricated in respective well...	04/11/2006
6967344	Multi-terminal chalcogenide switching devices Multi-terminal electronic switching devices comprising a chalcogenide material switchable between a resistive state and a conductive state. The devices include a first terminal, a second terminal and a control terminal. Application of a control signal to the control...	11/22/2005

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Class 257/260 - Same channel controlled by both junction and insulated gate electrodes, or by both Schottky barrier and pn junction gates (e.g., "taper isolated" memory cell)