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| Number | Title | Issue Date |
| 8134188 | Circuits and methods for improved FET matching Various embodiments of the present invention provide circuits and methods for improved FET matching. As one example, such methods may include providing two or more transistors. Each of the transistors includes a channel that varies in cross-sectional width from the ... | 03/13/2012 |
| 8058674 | Alternate 4-terminal JFET geometry to reduce gate to source capacitance A 4-Terminal JFET includes a substrate having a first conduction type and an upper layer having a second, opposite, conduction type over the substrate. A gate and a source are embedded in the upper layer. A gate pad is electrically connected to the gate. A region, w... | 11/15/2011 |
| 8035138 | Junction field effect transistor and production method for the same A junction field effect transistor of the present invention includes: a first conductivity type semiconductor substrate; a second conductivity type epitaxial layer formed on the semiconductor substrate; a first conductivity type epitaxial layer formed on the second ... | 10/11/2011 |
| 8035139 | Dynamic random access memory having junction field effect transistor cell access device A dynamic random access memory (DRAM) device can include a plurality of memory cells. Each memory cell can include a charge storing structure and an access device comprising an enhancement mode junction field effect transistor (JFET). The DRAM device can further inc... | 10/11/2011 |
| 7982248 | Junction field effect transistor, integrated circuit for switching power supply, and switching power supply A switching power supply has a start-up circuit that includes a field effect transistor (JFET), which has a gate region (a p-type well region) formed in a surface layer of a p-type substrate and a drift region (a first n-type well region). A plurality of source regi... | 07/19/2011 |
| 7973344 | Double gate JFET with reduced area consumption and fabrication method therefor Double gate JFET with reduced area consumption and fabrication method therefore. Double-gate semiconductor device including a substrate having a shallow trench isolator region comprising a first STI and a second STI, a channel region having a first and second channe... | 07/05/2011 |
| 7960763 | Semiconductor device and method of manufacturing the same A semiconductor device includes a substrate, a compound semiconductor layer formed over the substrate, and a protective insulating film composed of silicon nitride, which is formed over a surface of the compound semiconductor layer and whose film density in an inter... | 06/14/2011 |
| 7943971 | Junction field effect transistor (JFET) structure having top-to-bottom gate tie and method of manufacture A junction field effect transistor (JFET) can include a top gate structure and an active semiconductor region. The active semiconductor region can include a side surface and a top surface formed below the top gate structure. The active semiconductor region can also ... | 05/17/2011 |
| 7875910 | Integrated nitride and silicon carbide-based devices A monolithic electronic device includes a first nitride epitaxial structure including a plurality of nitride epitaxial layers. The plurality of nitride epitaxial layers include at least one common nitride epitaxial layer. A second nitride epitaxial structure is on t... | 01/25/2011 |
| 7772620 | Junction field effect transistor using a silicon on insulator architecture A junction field effect transistor comprises a silicon-on-insulator architecture. A front gate region and a back gate region are formed in a silicon region of the SOI architecture. The silicon region has a thin depth such that the back gate region has a thin depth, ... | 08/10/2010 |
| 7772619 | Semiconductor device having a fin structure and fabrication method thereof A semiconductor device includes a silicon on insulator (SOI) substrate, comprising an insulation layer formed on semiconductor material, and a fin structure. The fin structure is formed of semiconductor material and extends from the SOI substrate. Additionally, the ... | 08/10/2010 |
| 7755112 | Field effect transistor with air bridge A field effect transistor includes a channel region fabricated on a compound semiconductor substrate, a gate electrode fabricated on the channel region, a source electrode and a drain electrode alternately arranged on the channel region with a gate electrode interpo... | 07/13/2010 |
| 7692220 | Semiconductor device storage cell structure, method of operation, and method of manufacture The invention can include at least one storage cell having a store gate structure formed from a semiconductor material doped to a first conductivity type and in contact with a channel region comprising a semiconductor material doped to a second conductivity type. A ... | 04/06/2010 |
| 7687834 | Integrated circuit using complementary junction field effect transistor and MOS transistor in silicon and silicon alloys This invention describes a method of building complementary logic circuits using junction field effect transistors in silicon. This invention is ideally suited for deep submicron dimensions, preferably below 65 nm. The basis of this invention is a complementary Junc... | 03/30/2010 |
| 7655964 | Programmable junction field effect transistor and method for programming same A programmable junction field effect transistor (JFET) with multiple independent gate inputs. A drain, source and a plurality of gate regions for controlling a conductive channel between the source and drain are fabricated in a semiconductor substrate. A first porti... | 02/02/2010 |
| 7633100 | Phase change random access memory device A phase-change random access memory device includes a global bit line connected to a write circuit and a read circuit; a plurality of local bit lines, each of which being connected to a plurality of phase-change memory cells; and a plurality of column select transis... | 12/15/2009 |
| 7629630 | Electropolished patterned metal layer for semiconductor devices An electropolishing process for high resolution patterning of noble metals, such as platinum, for forming various semiconductor devices, such as capacitors or wiring patterns is disclosed. ... | 12/08/2009 |
| 7615809 | Junction field effect transistor and method of manufacturing the same According to a junction FET of the present invention, the depth of a channel region is made shallow by selectively performing ion implantation and diffusion. Since the channel region forms a pn junction together with a p type semiconductor layer with relatively low ... | 11/10/2009 |
| 7598547 | Low noise vertical variable gate control voltage JFET device in a BiCMOS process and methods to build this device We disclose the structure of a JFET device, the method of making the device and the operation of the device. The device is built near the top of a substrate. It has a buried layer that is electrically communicable to a drain terminal. It has a channel region over th... | 10/06/2009 |
| 7569873 | Integrated circuit using complementary junction field effect transistor and MOS transistor in silicon and silicon alloys This invention describes a method of building complementary logic circuits using junction field effect transistors in silicon. This invention is ideally suited for deep submicron dimensions, preferably below 65 nm. The basis of this invention is a complementary Junc... | 08/04/2009 |
| 7560755 | Self aligned gate JFET structure and method A JFET integrated onto a substrate having a semiconductor layer at least and having source and drain contacts over an active area and made of first polysilicon (or other conductors such as refractive metal or silicide) and a self-aligned gate contact made of second ... | 07/14/2009 |
| 7504676 | Planar split-gate high-performance MOSFET structure and manufacturing method This invention discloses an improved semiconductor power device includes a plurality of power transistor cells wherein each cell further includes a planar gate padded by a gate oxide layer disposed on top of a drift layer constituting an upper layer of a semiconduct... | 03/17/2009 |
| 7491987 | Junction field effect thin film transistor Example embodiments are directed to a junction field effect thin film transistor (JFETFT) including a first electrode formed on a substrate, a first conductive first gate semiconductor pattern formed on the first gate electrode, a second conductive semiconductor cha... | 02/17/2009 |
| 7479672 | Power junction field effect power transistor with highly vertical channel and uniform channel opening A semiconductor vertical junction field effect power transistor formed by a semiconductor structure having top and bottom surfaces and including a plurality of semiconductor layers with predetermined doping concentrations and thicknesses and comprising at least a bo... | 01/20/2009 |
| 7427544 | Semiconductor device and method of manufacturing the same A semiconductor device includes an element isolation insulating film provided in a semiconductor substrate between first and second element regions, a gate electrode running over the element isolation insulating film, first and second element regions, a first stoppe... | 09/23/2008 |
| 7411231 | JFET with drain and/or source modification implant The present invention provides a JFET which receives an additional implant during fabrication, which extends its drain region towards its source region, and/or its source region towards its drain region. The implant reduces the magnitude of the e-field that would ot... | 08/12/2008 |
| 7358122 | High performance FET devices and methods thereof Structure and methods of fabrication are disclosed for an enhanced FET devices in which dopant impurities are prevented from diffusing through the gate insulator. The structure comprises a Si:C, or SiGe:C, layer which is sandwiched between the gate insulator and a l... | 04/15/2008 |
| 7355223 | Vertical junction field effect transistor having an epitaxial gate A vertical junction field effect transistor includes a trench formed in an epitaxial layer. The trench surrounds a channel region of the epitaxial layer. The channel region may have a graded or uniform dopant concentration profile. An epitaxial gate structure is for... | 04/08/2008 |
| 7335952 | Semiconductor device and manufacturing method therefor To provide a semiconductor device that permits free setting of characteristics of individual semiconductor elements which are mixedly mounted and have different characteristics, and is free of steps between formed semiconductor elements, in a manufacturing method fo... | 02/26/2008 |
| 7323386 | Method of fabricating semiconductor device containing dielectrically isolated PN junction for enhanced breakdown characteristics A semiconductor device includes a field shield region that is doped opposite to the conductivity of the substrate and is bounded laterally by dielectric sidewall spacers and from below by a PN junction. For example, in a trench-gated MOSFET the field shield region m... | 01/29/2008 |
| 7321142 | Field effect transistor On an SiC single crystal substrate, an electric field relaxation layer and a p− type buffer layer are formed. The electric field relaxation layer is formed between the p− type buffer layer and the SiC single crystal substrate to contact SiC single crystal substr... | 01/22/2008 |
| 7312481 | Reliable high-voltage junction field effect transistor and method of manufacture therefor The present invention provides a high-voltage junction field effect transistor (JFET), a method of manufacture and an integrated circuit including the same. One embodiment of the high-voltage junction field effect transistor (JFET) (300) includes a well regio... | 12/25/2007 |
| 7304347 | Method for fabricating a power semiconductor device having a voltage sustaining layer with a terraced trench facilitating formation of floating islands A method is provided for forming a power semiconductor device. The method begins by providing a substrate of a first conductivity type and then forming a voltage sustaining region on the substrate. The voltage sustaining region is formed by depositing an epitaxial l... | 12/04/2007 |
| 7304335 | Vertical-conduction and planar-structure MOS device with a double thickness of gate oxide and method for realizing power vertical MOS transistors with improved static and dynamic performance and high scaling down density A vertical-conduction and planar-structure MOS device having a double thickness gate oxide includes a semiconductor substrate including spaced apart active areas in the semiconductor substrate and defining a JFET area therebetween. The JFET area also forms a channel... | 12/04/2007 |
| 7301741 | Integrated circuit with multiple independent gate field effect transistor (MIGFET) rail clamp circuit A rail clamp circuit (100) includes first and second power supply voltage rails, a multiple independent gate field effect transistor (MIGFET) (128), and an ESD event detector circuit (138). The MIGFET (128) has a source/drain path coupled... | 11/27/2007 |
| 7301185 | High-voltage transistor device having an interlayer dielectric etch stop layer for preventing leakage and improving breakdown voltage A high-voltage transistor device with an interlayer dielectric (ILD) etch stop layer for use in a subsequent contact hole process is provided. The etch stop layer is a high-resistivity film having a resistivity greater than 10 ohm-cm, thus leakage is prevented and b... | 11/27/2007 |
| 7279368 | Method of manufacturing a vertical junction field effect transistor having an epitaxial gate A vertical junction field effect transistor includes a trench formed in an epitaxial layer. The trench surrounds a channel region of the epitaxial layer. The channel region may have a graded or uniform dopant concentration profile. An epitaxial gate structure is for... | 10/09/2007 |
| 7268378 | Structure for reduced gate capacitance in a JFET A junction field effect transistor (JFET) with a reduced gate capacitance. A gate definition spacer is formed on the wall of an etched trench to establish the lateral extent of an implanted gate region for a JFET. After implant, the gate is annealed. In addition to ... | 09/11/2007 |
| 7265398 | Method and structure for composite trench fill A method and structure for a composite trench fill for silicon electronic devices. On a planar silicon substrate having a first deposited layer of oxide and a second deposited layer of polysilicon, a trench is etched. Deposition and etch processes using a combinatio... | 09/04/2007 |
| 7262461 | JFET and MESFET structures for low voltage, high current and high frequency applications JFET and MESFET structures, and processes of making same, for low voltage, high current and high frequency applications. The structures may be used in normally-on (e.g., depletion mode) or normally-off modes. The structures include an oxide layer positioned under th... | 08/28/2007 |
