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| Number | Title | Issue Date |
| 8159006 | Semiconductor device having a triple gate transistor and method for manufacturing the same In a semiconductor capable of reducing NBTI and a method for manufacturing the same, a multi-gate transistor includes an active region, gate dielectric, channels in the active region, and gate electrodes, and is formed on a semiconductor wafer. The active region has... | 04/17/2012 |
| 8148757 | Semiconductor device, and its manufacturing method A channel is formed at a recessed portion or a projecting portion of a substrate, and a gate insulating film is formed so as to have first to third insulating regions along the channel. Each of the gate insulating films of the first and third insulating regions has ... | 04/03/2012 |
| 8125007 | Integrated circuit including FinFET RF switch angled relative to planar MOSFET and related design structure An integrated circuit (IC) includes a fin field effect transistor (FinFET) radio frequency (RF) switch; and a planar complementary metal-oxide semiconductor field effect transistor (MOSFET). The planar MOSFET has a channel on a wafer plane and the FinFET RF sw... | 02/28/2012 |
| 8039878 | Transistor having a channel with tensile strain and oriented along a crystallographic orientation with increased charge carrier mobility By appropriately orienting the channel length direction with respect to the crystallographic characteristics of the silicon layer, the stress-inducing effects of strained silicon/carbon material may be significantly enhanced compared to conventional techniques. In o... | 10/18/2011 |
| 8039877 | (110)-oriented p-channel trench MOSFET having high-K gate dielectric A method of forming a field effect transistor having a heavily doped p-type (110) semiconductor layer over a metal substrate starts with providing a heavily doped p-type (110) silicon layer, and forming a lightly doped p-type (110) silicon layer on the P heavily dop... | 10/18/2011 |
| 8022444 | Biosensor and method of manufacturing the same Provided are a biosensor with a silicon nanowire and a method of manufacturing the same, and more particularly, a biosensor with a silicon nanowire including a defect region formed by irradiation of an electron beam, and a method of manufacturing the same. The biose... | 09/20/2011 |
| 8022445 | Method of manufacturing a semiconductor device A method of manufacturing a semiconductor device, including the steps of preparing a silicon substrate which has a main surface whose plane direction is a surface (100); forming an n channel MISFET (Metal Insulator Semiconductor Field Effect Transistor) which... | 09/20/2011 |
| 8008692 | Semiconductor memory structure with stress regions A semiconductor memory structure with stress regions includes a substrate defining a first and a second device zone; a first and a second stress region formed in each of the first and second device zone to yield stress different in level; a barrier plug separating t... | 08/30/2011 |
| 7985990 | Transistor layout for manufacturing process control A symmetrical circuit is disclosed (FIG. 4). The circuit includes a first transistor (220) having a first channel in a substantial shape of a parallelogram (FIG. 5A) with acute angles. The first transistor has a first current path (506) o... | 07/26/2011 |
| 7977712 | Asymmetric source and drain field effect structure A semiconductor structure, such as a CMOS semiconductor structure, includes a field effect device that includes a plurality of source and drain regions that are asymmetric. Such a source region and drain region asymmetry is induced by fabricating the semiconductor s... | 07/12/2011 |
| 7964899 | Semiconductor device and method for manufacturing the same for improving the performance of mis transistors An active region and an isolation region are formed in the surface of a silicon semiconductor substrate having a (100) crystal plane as a principal surface. A gate insulating film and a gate electrode are formed on the active region in this order. A stress control f... | 06/21/2011 |
| 7939862 | Stress-enhanced performance of a FinFet using surface/channel orientations and strained capping layers Different approaches for FinFET performance enhancement based on surface/channel direction and type of strained capping layer are provided. In one relatively simple and inexpensive approach providing a performance boost, a single surface/channel direction orientatio... | 05/10/2011 |
| 7906802 | Semiconductor element and a method for producing the same Some embodiments comprise a plurality of fins, wherein at least a first fin of the plurality of fins comprises a different fin width compared to a fin width of another fin of the plurality of fins. At least a second fin of the plurality of fins comprises a different... | 03/15/2011 |
| 7888710 | CMOS fabrication process utilizing special transistor orientation Complementary metal oxide semiconductor transistors are formed on a silicon substrate. The substrate has a {100} crystallographic orientation. The transistors are formed on the substrate so that current flows in the channels of the transistors are parallel to the | 02/15/2011 |
| 7842982 | Semiconductor device and manufacturing method thereof A semiconductor device includes a semiconductor substrate having, on a surface thereof, a (110) surface of Si1-xGex (0.25≦x≦0.90), and n-channel and p-channel MISFETs formed on the (110) surface, each MISFET having a source region, a channe... | 11/30/2010 |
| 7821044 | Transistor with improved tip profile and method of manufacture thereof Embodiments are an improved transistor structure and the method of fabricating the structure. In particular, a wet etch of an embodiment forms source and drain regions with an improved tip shape to improve the performance of the transistor by improving control of sh... | 10/26/2010 |
| 7772618 | Semiconductor storage device comprising MIS transistor including charge storage layer A semiconductor memory device includes a memory cell block. The memory cell block includes a plurality of n-type first MIS transistors with current passages connected in series. Each of the first MIS transistors includes a source, a drain, and a charge storage layer... | 08/10/2010 |
| 7728364 | Enhanced mobility CMOS transistors with a V-shaped channel with self-alignment to shallow trench isolation The present invention provides structures and methods for a transistor formed on a V-shaped groove. The V-shaped groove contains two crystallographic facets joined by a ridge. The facets have different crystallographic orientations than what a semiconductor substrat... | 06/01/2010 |
| 7696539 | Device fabrication by anisotropic wet etch A method of fabrication and a field effect device structure are presented that reduce source/drain capacitance and allow for device body contact. A Si based material pedestal is produced, the top surface and the sidewalls of which are oriented in a way to be substan... | 04/13/2010 |
| 7473946 | CMOS structure and method including multiple crystallographic planes A complementary metal oxide semiconductor (CMOS) structure includes a semiconductor substrate having first mesa having a first ratio of channel effective horizontal surface area to channel effective vertical surface area. The CMOS structure also includes a second me... | 01/06/2009 |
| 7456450 | CMOS devices with hybrid channel orientations and method for fabricating the same The present invention relates to a semiconductor substrate comprising at least first and second device regions, wherein the first device region comprises a first recess having interior surfaces oriented along a first set of equivalent crystal planes, and wherein the... | 11/25/2008 |
| 7423303 | Strained silicon directly-on-insulator substrate with hybrid crystalline orientation and different stress levels The present invention provides a strained Si directly on insulator (SSDOI) substrate having multiple crystallographic orientations and a method of forming thereof. Broadly, but in specific terms, the inventive SSDOI substrate includes a substrate; an insulating laye... | 09/09/2008 |
| 7372083 | Embedded silicon-controlled rectifier (SCR) for HVPMOS ESD protection A high voltage p-type metal oxide semiconductor (HVPMOS) device having electrostatic discharge (ESD) protection functions and a method of forming the same are provided. The HVPMOS includes a PMOS transistor, wherein the PMOS transistor comprises a first source/drain... | 05/13/2008 |
| 7368358 | Method for producing field effect device that includes epitaxially growing SiGe source/drain regions laterally from a silicon body A structure, and method of fabrication, for high performance field effect devices is disclosed. The MOS structures include a crystalline Si body of one conductivity type, a strained SiGe layer epitaxially grown on the Si body serving as a buried channel for holes, a... | 05/06/2008 |
| 7367119 | Method for forming a reinforced tip for a probe storage device Systems and methods in accordance with the present invention can include a tip contactable with a media. In an embodiment, the tip comprises a substantially hollow structure formed of a metal. The tip can be formed by depositing a first metal layer over silicon ther... | 05/06/2008 |
| 7368334 | Silicon-on-insulator chip with multiple crystal orientations A silicon-on-insulator chip includes an insulator layer, typically formed over a substrate. A first silicon island with a surface of a first crystal orientation overlies the insulator layer and a second silicon island with a surface of a second crystal orientation a... | 05/06/2008 |
| 7358552 | Complementary metal-oxide-semiconductor image sensor and method for fabricating the same A complementary metal-oxide-semiconductor (CMOS) image sensor and a method for fabricating the same are provided. The CMOS image sensor includes: a pixel region provided with a plurality of unit pixels, each including a buried photodiode and a floating diffusion reg... | 04/15/2008 |
| 7348658 | Multilayer silicon over insulator device An apparatus and method for a multilayer silicon over insulator (SOI) device is provided. In the multilayer SOI device, the crystal orientation of at least one active region of a device is different than the active region of at least another device. Where the multil... | 03/25/2008 |
| 7339213 | Semiconductor device having a triple gate transistor and method for manufacturing the same In a semiconductor capable of reducing NBTI and a method for manufacturing the same, a multi-gate transistor includes an active region, gate dielectric, channels in the active region, and gate electrodes, and is formed on a semiconductor wafer. The active region has... | 03/04/2008 |
| 7335942 | Field effect transistor sensor The invention relates to a sensor, especially for the probe of a screen probe microscope, for examining probe surfaces (40) or areas adjacent to the sensor, comprising at least one field effect transistor (FET) made of at least one semiconductor material. The... | 02/26/2008 |
| 7336524 | Atomic probes and media for high density data storage A device in accordance with embodiments of the present invention comprises a contact probe for high density data storage reading, writing, erasing, or rewriting. In one embodiment, the contact probe can include a silicon core having a conductive coating. Contact pro... | 02/26/2008 |
| 7332384 | Technique for forming a substrate having crystalline semiconductor regions of different characteristics Different types of crystalline semiconductor regions are provided on a single substrate by forming a dielectric region within a first crystalline semiconductor region. Thereafter, a second crystalline region is positioned above the dielectric region by wafer bond te... | 02/19/2008 |
| 7329923 | High-performance CMOS devices on hybrid crystal oriented substrates An integrated semiconductor structure containing at least one device formed upon a first crystallographic surface that is optimal for that device, while another device is formed upon a second different crystallographic surface that is optimal for the other device is... | 02/12/2008 |
| 7312485 | CMOS fabrication process utilizing special transistor orientation Complementary metal oxide semiconductor transistors are formed on a silicon substrate. The substrate has a {100} crystallographic orientation. The transistors are formed on the substrate so that current flows in the channels of the transistors are parallel to the | 12/25/2007 |
| 7309630 | Method for forming patterned media for a high density data storage device Systems in accordance with the present invention can include a tip contactable with a media, the media including a substrate and a plurality of cells disposed over the substrate, one or more of the cells being electrically isolated from the other of the cells by a m... | 12/18/2007 |
| 7301185 | High-voltage transistor device having an interlayer dielectric etch stop layer for preventing leakage and improving breakdown voltage A high-voltage transistor device with an interlayer dielectric (ILD) etch stop layer for use in a subsequent contact hole process is provided. The etch stop layer is a high-resistivity film having a resistivity greater than 10 ohm-cm, thus leakage is prevented and b... | 11/27/2007 |
| 7298009 | Semiconductor method and device with mixed orientation substrate A semiconductor device includes a semiconductor body having semiconductor material of a first crystal orientation. A first transistor is formed in the semiconductor material of the first crystal orientation. An insulating layer overlies portions of the semiconductor... | 11/20/2007 |
| 7288821 | Structure and method of three dimensional hybrid orientation technology A method and device for increasing pFET performance without degradation of nFET performance. The method includes forming a first structure on a substrate using a first plane and direction and forming a second structure on the substrate using a second plane and direc... | 10/30/2007 |
| 7288458 | SOI active layer with different surface orientation A wafer having an SOI configuration and active regions having different surface orientations for different channel type transistors. In one example, semiconductor structures having a first surface orientation are formed on a donor wafer. Semiconductor structures hav... | 10/30/2007 |
| 7268399 | Enhanced PMOS via transverse stress In the present invention, a PMOS device comprises a channel region formed in {100} silicon with first and second source/drain region disposed on either side of the channel region. The channel region is oriented such that a current flow between the source/drain regio... | 09/11/2007 |
