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| Number | Title | Issue Date |
| 8164122 | Thin film field effect transistor with dual semiconductor layers A thin film field effect transistor is disclosed which provides improved time-based channel stability. The field effect transistor includes first and second disordered semiconductor layers separated by an insulator. In an embodiment a carrier injection terminal is p... | 04/24/2012 |
| 8053818 | Thin film field effect transistor with dual semiconductor layers A thin film field effect transistor is disclosed which provides improved time-based channel stability. The field effect transistor includes first and second disordered semiconductor layers separated by an insulator. In an embodiment a carrier injection terminal is p... | 11/08/2011 |
| 7923759 | Metal gate semiconductor device and manufacturing method A method for manufacturing a metal gate includes providing a substrate including a gate electrode located on the substrate. A plurality of layers is formed, including a first layer located on the substrate and the gate electrode and a second layer adjacent the first... | 04/12/2011 |
| 7808019 | Gate structure A gate structure includes a substrate, a gate dielectric layer, a first conductive layer, a second conductive layer, a cap layer and a first insulating spacer. The gate dielectric layer is disposed on the substrate. The first conductive layer is disposed on the gate... | 10/05/2010 |
| 7781807 | Non-volatile semiconductor storage device A three-dimensional non-volatile semiconductor storage device which realizes both increased packing density and improved performance is disclosed. According to one aspect, there is provided a non-volatile semiconductor storage device comprising a first non-volatile ... | 08/24/2010 |
| 7586135 | Multilevel integrated circuit devices and methods of forming the same Semiconductor devices including a plurality of semiconductor layers. A plurality of transistors are on each of the semiconductor layers. The transistors include gate lines and have source regions and drain regions formed between the gate lines in the respective semi... | 09/08/2009 |
| 7525135 | Semiconductor device and display device On a poly-silicon layer formed on a glass substrate, a gate electrode is formed via a gate insulation film. After forming an impurity-doped region in the poly-silicon layer using the gate electrode as a mask, an insulation layer is formed on the gate electrode and a... | 04/28/2009 |
| 7449733 | Semiconductor device and method of fabricating the same A semiconductor device includes a semiconductor substrate, a channel region formed above the semiconductor substrate, a first gate electrode formed above the channel region via a first gate insulating film, a second gate electrode formed below the channel region via... | 11/11/2008 |
| 7446353 | Solid-state imaging apparatus and charge transfer apparatus A solid-state imaging apparatus includes a photoelectric conversion section generating a charge by photoelectric conversion; and a charge transfer section having first and second transfer electrodes arranged in parallel with each other in an output direction of a ch... | 11/04/2008 |
| 7425473 | Method of fabricating a thin film transistor for an array panel A method for making a thin film transistor, TFT, (306) on a substrate includes a photolithographic process step of patterning three layers of materials to form a TFT (306) and to form a bridging structure (308) crossing over a TFT gate bus-line ... | 09/16/2008 |
| 7385249 | Transistor structure and integrated circuit A process for forming a conductive gate structure for a sub-0.25 MOSFET technology, has been developed. The process features a conductive gate structure defined from a composite polysilicon or amorphous layer, which in turn is obtained via a dual deposition procedur... | 06/10/2008 |
| 7372086 | Semiconductor device including MOSFET and isolation region for isolating the MOSFET A semiconductor device comprises a semiconductor substrate, a MOSFET including a double gate structure provided on the semiconductor substrate, and an isolation region for isolating the MOSFET from other elements comprising a trench provided on the surface of the se... | 05/13/2008 |
| 7359010 | Method for producing display device In a liquid crystal display device, a first substrate includes electrical wirings and a semiconductor integrated circuit which has TFTs and is connected electrically to the electrical wirings, and a second substrate includes a transparent conductive film on a surfac... | 04/15/2008 |
| 7352034 | Semiconductor structures integrating damascene-body FinFET's and planar devices on a common substrate and methods for forming such semiconductor structures Methods of forming a semiconductor structure having FinFET's and planar devices, such as MOSFET's, on a common substrate by a damascene approach. A semiconductor fin of the FinFET is formed on a substrate with damascene processing in which the fin growth may be inte... | 04/01/2008 |
| 7348636 | CMOS transistor having different PMOS and NMOS gate electrode structures and method of fabrication thereof In a CMOS semiconductor device using a silicon germanium gate and a method of fabricating the same, a gate insulating layer, a conductive electrode layer that is a seed layer, a silicon germanium electrode layer, and an amorphous conductive electrode layer are seque... | 03/25/2008 |
| 7342264 | Memory cell and method for manufacturing the same The invention is directed to a memory cell on a substrate having a plurality of shallow trench isolations form therein, wherein top surfaces of the shallow trench isolations are lower than a top surface of the substrate and the shallow trench isolations together def... | 03/11/2008 |
| 7338862 | Methods of fabricating a single transistor floating body DRAM cell having recess channel transistor structure Methods of fabricating a single transistor floating body dynamic random access memory (DRAM) cell include forming a barrier layer on a semiconductor substrate. A body layer is formed on the barrier layer. An isolation layer is formed defining a floating body region ... | 03/04/2008 |
| 7326634 | Bulk non-planar transistor having strained enhanced mobility and methods of fabrication A method of a bulk tri-gate transistor having stained enhanced mobility and its method of fabrication. The present invention is a nonplanar transistor having a strained enhanced mobility and its method of fabrication. The transistor has a semiconductor body formed o... | 02/05/2008 |
| 7312486 | Stripe board dummy metal for reducing coupling capacitance Dishing is known to be a problem after CMP of dielectric layers in which the distribution of embedded metal is non-uniform. This problem has been solved by populating those areas where the density of embedded metal is low with unconnected regions that, instead of be... | 12/25/2007 |
| 7288805 | Double gate isolation A double-gated fin-type field effect transistor (FinFET) structure has electrically isolated gates. In a method for manufacturing the FinFET structure, a fin, having a gate dielectric on each sidewall corresponding to the central channel region, is formed over a bur... | 10/30/2007 |
| 7288823 | Double gate field effect transistor and method of manufacturing the same Provided is a double gate field effect transistor and a method of manufacturing the same. The method of manufacturing the double gate field effect transistor includes forming as many fins as required by etching a silicon substrate, masking the resultant product by a... | 10/30/2007 |
| 7274053 | Fin device with capacitor integrated under gate electrode A fin-type field effect transistor (FinFET) has a fin having a center channel portion, end portions comprising source and drain regions, and channel extensions extending from sidewalls of the channel portion of the fin. The structure also includes a gate insulator c... | 09/25/2007 |
| 7268379 | Memory cell and method for manufacturing the same The invention is directed to a memory cell on a substrate having a plurality of shallow trench isolations form therein, wherein top surfaces of the shallow trench isolations are lower than a top surface of the substrate and the shallow trench isolations together def... | 09/11/2007 |
| 7265432 | Solid state imaging device and method of fabricating the same A method for fabricating a solid state imaging device comprising photoelectric conversion sections and charge transfer sections having single-layered charge transfer electrodes for transferring charges generated in the photoelectric conversion sections, the method i... | 09/04/2007 |
| 7264846 | Ruthenium layer formation for copper film deposition A method of ruthenium layer formation for high aspect ratios, interconnect features is described. The ruthenium layer is formed using a cyclical deposition process. The cyclical deposition process comprises alternately adsorbing a ruthenium-containing precursor and ... | 09/04/2007 |
| 7265397 | CCD imager constructed with CMOS fabrication techniques and back illuminated imager with improved light capture An optical sensor circuit for generating signals corresponding to received photoelectrons is formed on a single monolithic substrate and includes a charge coupled device (CCD) array. The array is formed of a plurality of pixels constructed by a standard CMOS process... | 09/04/2007 |
| 7259049 | Self-aligned isolation double-gate FET A double-gate field effect transistor (DGFET) structure and method of forming such a structure in which the parasitic capacitance under the source/drain regions is substantially reduced are provided. Two new means to reduce the parasitic capacitance under the source... | 08/21/2007 |
| 7256830 | Solid-state imaging device and manufacturing method for solid-state imaging device A solid-state imaging device comprises a semi-conductor substrate demarcating a two-dimensional surface, a multiplicity of photoelectric conversion units formed at grid points of a first grid of a first tetragonal matrix and a second tetragonal matrix having grid po... | 08/14/2007 |
| 7253033 | Method of manufacturing a semiconductor device that includes implanting in multiple directions a high concentration region In a complete depletion type SOI transistor, the roll-off of a threshold value is suppressed, independently from the formation of an SOI film to be thinner. As for a semiconductor device (1), the impurity concentration in a channel formation portion (10 | 08/07/2007 |
| 7253043 | Short channel semiconductor device fabrication The formation of one or more accumulation mode multi gate transistor devices is disclosed. The devices are formed so that short channel effects are mitigated. In particular, one more types of dopant materials are implanted in a channel region, an extension region an... | 08/07/2007 |
| 7208794 | High-density NROM-FINFET Semiconductor memory having memory cells, each including first and second conductively-doped contact regions and a channel region arranged between the latter, formed in a web-like rib made of semiconductor material and arranged one behind the other in this sequence ... | 04/24/2007 |
| 7205185 | Self-aligned planar double-gate process by self-aligned oxidation A double-gate transistor has front (upper) and back gates aligned laterally by a process of forming symmetric sidewalls in proximity to the front gate and then oxidizing the back gate electrode at a temperature of at least 1000 degrees for a time sufficient to relie... | 04/17/2007 |
| 7199409 | Device for subtracting or adding charge in a charge-coupled device The present invention provides an apparatus for adding or subtracting an amount charge to or from a charge packet in a CCD as the packet traverses the CCD. The apparatus uses a “wire transfer” device structure to perform the addition or subtraction of charge dur... | 04/03/2007 |
| 7176092 | Gate electrode for a semiconductor fin device A method for forming a gate electrode for a multiple gate transistor provides a doped, planarized gate electrode material which may be patterned using conventional methods to produce a gate electrode that straddles the active area of the multiple gate transistor and... | 02/13/2007 |
| 7164161 | Method of formation of dual gate structure for imagers A device, as in an integrated circuit, includes diverse components such as transistors and capacitors. After conductive layers for all types of components are produced, a silicide layer is provided over conductive layers, reducing resistance. The device can be an im... | 01/16/2007 |
| 7163864 | Method of fabricating semiconductor side wall fin A double gated silicon-on-insulator (SOI) MOSFET is fabricated by forming epitaxially grown channels, followed by a damascene gate. The double gated MOSFET features narrow channels, which increases current drive per layout width and provides low out conductance.... | 01/16/2007 |
| 7161827 | SRAM having improved cell stability and method therefor A SRAM (14) includes a SRAM cell (26), the cell (26) includes a first storage node (N1), a second storage node (N2), and a cross coupled latch (40) including a first primary source current path to the first storage node, a f... | 01/09/2007 |
| 7154549 | Solid state image sensor having a single-layered electrode structure Provided is a CCD image sensor wherein driving power and power consumption are reduced without increasing unusable regions. Photodiodes are arranged in a honeycomb form. Each vertical charge-transfer channel is made in such a manner that invasion portions, which inv... | 12/26/2006 |
| 7154135 | Double-gated transistor circuit An OR gate circuit includes double-gated four terminal transistor with independent gate control. First and second inputs are independently coupled to the top and bottom gates of the transistor. The drain is coupled to an output and precharged to a low voltage. An in... | 12/26/2006 |
| 7154118 | Bulk non-planar transistor having strained enhanced mobility and methods of fabrication A method of a bulk tri-gate transistor having stained enhanced mobility and its method of fabrication. The present invention is a nonplanar transistor having a strained enhanced mobility and its method of fabrication. The transistor has a semiconductor body formed o... | 12/26/2006 |
