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| Number | Title | Issue Date |
| 8120070 | Wiring board and method for manufacturing the same A wiring board with an electronic device comprising a plurality of trenches arranged in parallel on a substrate, a common trench communicating the plurality of trenches with each other at one of their ends on the substrate, a metal layer formed at the bottom of the ... | 02/21/2012 |
| 7700979 | Semiconductor device having bulb-shaped recess gate and method for fabricating the same A semiconductor device includes: a substrate; a first junction region and a second junction region formed separately from each other in the substrate; an etch barrier layer formed in the substrate underneath the first junction region; and a plurality of recess chann... | 04/20/2010 |
| 7479670 | Organic electronic component with high resolution structuring, and method of the production thereof The invention relates to an electronic component made primarily from organic materials with high resolution structuring, in particular to an organic field effect transistor (OFET) with a small source-drain distance, and to a production method thereof. The organic el... | 01/20/2009 |
| 7442984 | Semiconductor memory device and manufacturing method thereof An active region is provided which includes a plurality of active region columns extending in a first direction and a plurality of active region rows extending in a second direction substantially orthogonal to the first direction and having concave portions. Floatin... | 10/28/2008 |
| 7436009 | Via structures and trench structures and dual damascene structures Via hole and trench structures and fabrication methods are disclosed. The structure includes a conductive layer in a dielectric layer, and a via structure in the dielectric layer contacting a portion of a surface of the conductive layer. The via structure includes t... | 10/14/2008 |
| 7436030 | Strained MOSFETs on separated silicon layers A method of fabricating and a structure of an IC incorporating strained MOSFETs on separated silicon layers are disclosed. N-channel field effect transistors (nFET) and P-channel FETs (pFET) are formed on the separated silicon layers, respectively. Shallow trench in... | 10/14/2008 |
| 7425751 | Method to reduce junction leakage current in strained silicon on silicon-germanium devices A MOSFET device in strained silicon-on-SiGe and a method of forming the device are described. The said device achieves reduced junction leakage due to the lower band-gap values of SiGe. The method consists of forming isolation trenches in a composite strained-Si/SiG... | 09/16/2008 |
| 7369736 | Light tunnel, uniform light illuminating device and projector employing the same Provided is a light tunnel including a guide member for guiding an incident light to proceed therein while being reflected by a side wall thereof to merge the incident light into a uniform light beam, and an optical path change portion provided at least one end port... | 05/06/2008 |
| 7345350 | Process and integration scheme for fabricating conductive components, through-vias and semiconductor components including conductive through-wafer vias A method for forming a conductive via in a semiconductor component is disclosed. The method includes providing a substrate having a first surface and an opposing, second surface. At least one hole is formed in the substrate extending between the first surface and th... | 03/18/2008 |
| 7323383 | Method for fabricating an NROM memory cell arrangement In the method, trenches (9) are etched and, in between, bit lines (8) are in each case arranged on doped source drain/regions (3). Dopant is introduced into the bottoms of the trenches (9) in order to form doped regions (23), in or... | 01/29/2008 |
| 7323720 | Light-emitting device, image forming apparatus, and electronic apparatus with an integrated circuit mounted on a substrate A light-emitting device includes a substrate having a plurality of light-emitting elements and a light emission region arranged on one surface thereof, light being emitted from one surface of the light emission region; and an integrated circuit chip that generates s... | 01/29/2008 |
| 7279766 | Photodiode sensor and photosensor for use in an imaging device A multiple-trench photosensor for use in a CMOS imager having an improved charge capacity. The multi-trench photosensor may be either a photogate or photodiode structure. The multi-trench photosensor provides the photosensitive element with an increased surface area... | 10/09/2007 |
| 7253493 | High density access transistor having increased channel width and methods of fabricating such devices A memory device having decreased cell size and having transistors with increased channel widths. More specifically, pillars are formed in a substrate such that sidewalls are exposed. The sidewalls of the pillars and the top surface of the pillars are covered with a ... | 08/07/2007 |
| 7250321 | Method of forming a photosensor A trench photosensor for use in a CMOS imager having an improved charge capacity. The trench photosensor may be either a photogate or photodiode structure. The trench shape of the photosensor provides the photosensitive element with an increased surface area compare... | 07/31/2007 |
| 7242823 | Optical transmission channel board, board with built-in optical transmission channel, and data processing apparatus An optical transmission board is provided. The optical transmission board includes an optical transmission channel, a retention board for retaining the optical transmission channel and circuit patterns. The circuit patterns are formed on the retention board and a pa... | 07/10/2007 |
| 7190050 | Integrated circuit on corrugated substrate By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a “corrugated substrate”), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-powe... | 03/13/2007 |
| 7187018 | Reduced barrier photodiode/transfer gate device structure of high efficiency charge transfer and reduced lag and method of formation A pixel cell having a reduced potential barrier near a region where a gate and a photodiode are in close proximity to one another, and a method for forming the same are disclosed. Embodiments of the invention provide a pixel cell comprising a substrate. A gate of a ... | 03/06/2007 |
| 7141486 | Shallow trench isolation structures comprising a graded doped sacrificial silicon dioxide material and a method for forming shallow trench isolation structures A shallow trench isolation structure having a negative taper angle. A graded doped sacrificial layer is formed over a semiconductor substrate and etched to form a first trench therein having trench sidewalls that present a negative taper angle. The substrate is also... | 11/28/2006 |
| 7109557 | Sacrificial dielectric planarization layer A method of forming a microelectronic structure and its associated structures is described. In one embodiment, a substrate is provided with a sacrificial layer disposed on a hard mask layer, and a metal layer disposed in a trench of the substrate and on the sacrific... | 09/19/2006 |
| 7098105 | Methods for forming semiconductor structures The invention includes a semiconductor structure having a gateline lattice surrounding vertical source/drain regions. In some aspects, the source/drain regions can be provided in pairs, with one of the source/drain regions of each pair extending to a digit line and ... | 08/29/2006 |
| 7045874 | Micromechanical strained semiconductor by wafer bonding One aspect disclosed herein relates to a method for forming a strained semiconductor structure. In various embodiments of the method, a number of recesses are formed in a surface of a first semiconductor wafer such that the surface of the first semiconductor wafer h... | 05/16/2006 |
| 6992340 | Semiconductor device A semiconductor device includes spaced-apart first and second element formation regions which are formed in a main surface of a semiconductor substrate, a dielectric film which is formed on the main surface of the semiconductor substrate at a location between the fi... | 01/31/2006 |
| 6906419 | Semiconductor device having a wiring layer of damascene structure and method for manufacturing the same In a semiconductor device, a wiring pattern groove is formed in a surface portion of a silicon oxide film provided above a semiconductor substrate. A wiring layer is buried into the wiring pattern groove with a barrier metal film interposed therebetween. The barrier... | 06/14/2005 |
| 6876034 | Semiconductor device having active grooves A semiconductor device having grooves uniformly filled with semiconductor fillers is provided. Both ends of each of narrow active grooves are connected to an inner circumferential groove surrounding the active grooves. The growth speed of semiconductor fillers on bo... | 04/05/2005 |
| 6828606 | Substrate with embedded free space optical interconnects Substrates with embedded free space light guiding channels for optical interconnects, and methods for making such substrates are shown. The method comprising steps of a groove in a first generally planar body, and combining the first body with a second generally pla... | 12/07/2004 |
| 6818949 | Semiconductor device and method for fabricating the same Described is a method for fabricating a semiconductor device having an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of ... | 11/16/2004 |
| 6812508 | Semiconductor substrate and method for fabricating the same A semiconductor substrate device comprises a first semiconductor substrate including a concave-convex surface and a second semiconductor substrate having an insulating film on a surface thereof. The first semiconductor substrate and the second semiconductor substrat... | 11/02/2004 |
| 6806805 | Low loss high Q inductor A high Q inductive clement with low losses, high inductance and high efficiency is disclosed. The high Q inductive element with one or more inductive loops is formed over a silicon micro structure with thin support elements formed by deep plasma etching in bulk sili... | 10/19/2004 |
| 6777725 | NROM memory circuit with recessed bitline An integrated memory circuit of the type of an NROM memory includes recessed bit lines formed of a material having a low ohmic resistance. By recessing the bit lines with respect to the semiconductor substrate surface of a peripheral controlling circuit for an array... | 08/17/2004 |
| 6777726 | MOSFET source, drain and gate regions in a trench between a semiconductor pillar and filling insulation In a metal oxide semiconductor (MOS) field effect transistor configuration, a source, a drain and a gate are embedded between a semiconductor pillar that extends away from a semiconductor body and forms a body region. A filling insulator surrounds the semiconductor ... | 08/17/2004 |
| 6774415 | Method and structure for ultra-thin film SOI isolation A method and structure for fabricating isolation regions on a silicon on insulator (SOI) substrate, wherein the SOI substrate comprises a buried oxide layer and a silicon layer disposed on the buried oxide layer, wherein the silicon layer is less than about 20 nanom... | 08/10/2004 |
| 6762443 | Vertical transistor and transistor fabrication method In DRAM memory cells, individual memory cells are isolated from one another by an isolation trench (STI). In such a case, a vertical transistor is formed by the isolation trench as SOI transistor because its channel region is isolated from a substrate by the isolati... | 07/13/2004 |
| 6664592 | Semiconductor device with groove type channel structure A semiconductor device includes a semiconductor substrate, a gate insulator film formed on a bottom surface and a side surface of a groove formed in the semiconductor substrate, a gate electrode having a lower portion buried in the groove on whose bottom ... | 12/16/2003 |
| 6597053 | Integrated circuit arrangement with a number of structural elements and method for the production thereof An integrated circuit arrangement having a number of structural elements, at least one of which is surrounded by a metallic shielding structure. This structural element is thus protected against interference due to disturbing impulses from its environment... | 07/22/2003 |
| 6570196 | Lipid vesicles or lipid bilayers on chips The present invention relates to bioelectronic devices comprising lipid vesicles which are in contact with a chip, particularly with at least one gate of a field effect transistor. The vesicles/bilayers may comprise effector molecules in their membrane an... | 05/27/2003 |
| 6570220 | Fabrication of deep submicron structures and quantum wire transistors using hard-mask transistor width definition The invention relates to a method of forming reduced feature size spacers. The method includes providing a semiconductor substrate having an area region; patterning a first spacer over a portion of the area region of the substrate, the first spacer having... | 05/27/2003 |
| 6545302 | Image sensor capable of decreasing leakage current between diodes and method for fabricating the same An image sensor capable of preventing the degradation of pinned photodiodes and the generation of leakage current between neighboring pinned photodiodes is provided. The disclosed image sensor contains a plurality of pixel units, each pixel unit having a ... | 04/08/2003 |
| 6515317 | Sidewall charge-coupled device with multiple trenches in multiple wells Increased pixel density and increased sensitivity to blue light are provided in a charge couple device employing sidewall and surface gates.... | 02/04/2003 |
| 6498379 | Semiconductor device and method for fabricating same A semiconductor device and a method for fabricating the same which improve characteristic of stand-by current of an SRAM cell is disclosed in the present invention. The semiconductor device comprises a semiconductor substrate in which a peripheral area an... | 12/24/2002 |
| 6498381 | Semiconductor structures having multiple conductive layers in an opening, and methods for fabricating same In some embodiments, a circuit structure comprises a semiconductor substrate, an opening passing through the substrate between a first side of the substrate and a second side of the substrate, and a plurality of conductive layers in the opening. In some e... | 12/24/2002 |
