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| Number | Title | Issue Date |
| 8164121 | Charge coupled device with potential gradient region between two control gate regions A six-phase charge coupled device (CCD) pixel includes a pixel pair, with each pixel having two adjacent control gates overlying corresponding variable potential wells, where voltages applied to the control gates enable charge to be accumulated into and transferred ... | 04/24/2012 |
| 7719036 | Charge coupled device with high quantum efficiency A six-phase charge coupled device (CCD) pixel includes a pixel pair, with each pixel having two adjacent control gates overlying corresponding variable potential wells, where voltages applied to the control gates enable charge to be accumulated into and transferred ... | 05/18/2010 |
| 7387908 | CMOS imager with enhanced transfer of charge and low voltage operation and method of formation A dopant gradient region of a first conductivity type and a corresponding channel impurity gradient below a transfer gate and adjacent a charge collection region of a CMOS imager photodiode are disclosed. The channel impurity gradient in the transfer gate provides a... | 06/17/2008 |
| 7378714 | Semiconductor device and its manufacturing method In a complete depletion type SOI transistor, the roll-off of a threshold value is suppressed, independently from the formation of an SOI film to be thinner. As for a semiconductor device (1), the impurity concentration in a channel formation portion (10 | 05/27/2008 |
| 7329926 | Semiconductor device with constricted current passage A semiconductor device including a gate located over a semiconductor substrate and a source/drain region located adjacent the gate. The source/drain region is bounded by an isolation structure that includes a constricted current passage between the gate and the sour... | 02/12/2008 |
| 7304354 | Buried guard ring and radiation hardened isolation structures and fabrication methods Semiconductor devices can be fabricated using conventional designs and process but including specialized structures to reduce or eliminate detrimental effects caused by various forms of radiation. Such semiconductor devices can include the one or more parasitic isol... | 12/04/2007 |
| 7265397 | CCD imager constructed with CMOS fabrication techniques and back illuminated imager with improved light capture An optical sensor circuit for generating signals corresponding to received photoelectrons is formed on a single monolithic substrate and includes a charge coupled device (CCD) array. The array is formed of a plurality of pixels constructed by a standard CMOS process... | 09/04/2007 |
| 7157754 | Solid-state imaging device and interline transfer CCD image sensor A high-performance solid-state imaging device is provided. The solid-state imaging device includes: a plurality of pixel cells; and a driving unit. Each of the plurality of pixel cells includes: a photodiode that converts incident light into a signal charge and stor... | 01/02/2007 |
| 7138670 | Semiconductor device for use in a solid state imaging device A compact semiconductor device having a contact hole that improves stability of electric connection between a wire and an electrode. The semiconductor device includes an insulation layer formed on a semiconductor substrate, first electrodes formed on the insulation ... | 11/21/2006 |
| 7119379 | Semiconductor device A semiconductor device disclosed herein comprises: a first base region which is of a first conductivity type; a second base region which is of a second conductivity type and which is selectively formed on a major surface of the first base region; a stopper region wh... | 10/10/2006 |
| 7119356 | Forming closely spaced electrodes The present invention provides an apparatus and a method of fabricating the apparatus. The apparatus comprises a substrate having a planar surface and first and second electrodes located on the planar surface. The first electrode has a top surface and a lateral surf... | 10/10/2006 |
| 7078745 | CMOS imager with enhanced transfer of charge and low voltage operation A dopant gradient region of a first conductivity type and a corresponding channel impurity gradient below a transfer gate and adjacent a charge collection region of a CMOS imager photodiode are disclosed. The channel impurity gradient in the transfer gate provides a... | 07/18/2006 |
| 7075128 | Charge transfer element having high output sensitivity A charge transfer element comprising a reverse conductive type well formed on the surface of one conductive type semiconductor substrate, the one conductive type channel region extending in one direction relative to the well, a transfer electrode formed intersecting... | 07/11/2006 |
| 6949777 | Method of controlling insulated gate transistor An insulated gate transistor is comprised of a semiconductor thin film, a first gate insulating film formed on a main surface of the semiconductor thin film, a first conductive gate formed on the first gate insulating film, first and second confronting semiconductor... | 09/27/2005 |
| 6924472 | Image sensor with improved optical response uniformity An image sensor includes a semiconductor substrate; a photosensor having, a first photosensing region including a first stack of one or more layers of transparent materials covering the substrate, the first photosensing region having a spectral response having minim... | 08/02/2005 |
| 6909126 | Imager cell with pinned transfer gate An imager cell includes a photoreceptor, a sense node, and a pinned transfer gate. The pinned transfer gate is tied to the same potential of a substrate of the imager cell and is disposed between the photoreceptor and the sense node in order to transfer charge betwe... | 06/21/2005 |
| 6867438 | Solid-state imaging device and manufacturing method thereof There is a demand of a solid-state imaging device capable of being driven at a high speed and in which the shading of sensitivity and illuminance defect can be prevented from being caused. A solid-state imaging device (20) comprises a light-receiving sensor s... | 03/15/2005 |
| 6847065 | Radiation-hardened transistor fabricated by modified CMOS process An NMOS field effect transistor (1) is made radiation hard by a pair of guard band implants (115) of limited horizontal extent, extending between the source (30A) and drain (30B) along the edge of the transistor body, and extending only t... | 01/25/2005 |
| 6787829 | LCD panel A liquid crystal display panel of the invention is such that, in a pixel region defined by a region of the array substrate surrounded by a pair of image signal lines and a pair of scanning signal lines, of a line-shaped pixel electrode and a common electrode, the el... | 09/07/2004 |
| 6762441 | Imager cell with pinned transfer gate An imager cell includes a photoreceptor, a sense node, and a pinned transfer gate. The pinned transfer gate is disposed to transfer charge between the photoreceptor and the sense node. The imager further includes a reset transistor disposed to reset the sense node, ... | 07/13/2004 |
| 6744083 | Submicron MOSFET having asymmetric channel profile A MOSFET semiconductor device having an asymmetric channel region between the source region and the drain region. In one embodiment, the device comprises a mesa structure on a silicon substrate with the source region being in the substrate and the mesa structure ext... | 06/01/2004 |
| 6657243 | Semiconductor device with SRAM section including a plurality of memory cells A semiconductor device having an SRAM section in which a p-well, a first n-well, and a second n-well are formed in a semiconductor substrate. Two n-type access transistors and two n-type driver transistors are formed in the p-well. Two p-type load transis... | 12/02/2003 |
| 6645839 | Method for improving a doping profile for gas phase doping A method for improving a doping profile using gas phase doping is described. In the method, silicon nitride and/or products of decomposition from a silicon nitride deposition are introduced in a process chamber before or during the actual gas phase doping... | 11/11/2003 |
| 6639259 | Charge-coupled device The invention relates to a CCD of the buried-channel type comprising a charge-transport channel in the form of a zone (12) of the first conductivity type, for example the n-type, in a well (13) of the opposite conductivity type, in the example the p-type.... | 10/28/2003 |
| 6603144 | Solid-state imaging device and method for fabricating same P-type ion implantation is done in N well 15, so as to form a charge drain control layer 17 and form a photodiode N well 16 and OFD drain 5, the result being that, even if there is variation in the potential of the photodiode N well 16 making up the photo... | 08/05/2003 |
| 6590241 | MOS transistors with improved gate dielectrics The specification describes silicon MOS devices with gate dielectrics having the composition Ta1-x Alx Oy, where x is 0.03-0.7 and y is 1.5-3, Ta1-x Six Oy, where x is 0.05-0.15, and y is 1... | 07/08/2003 |
| 6586784 | Accumulation mode clocking of a charge-coupled device A method for reducing dark current within a charge coupled device includes the steps of providing three or more phases of gates separated by an insulating layer from a buried channel of the first conductivity type in a well or substrate of the second cond... | 07/01/2003 |
| 6583474 | Semiconductor device There is provided a semiconductor device having a new structure which allows a high reliability and a high field effect mobility to be realized in the same time. In an insulated gate transistor having an SOI structure utilizing a mono-crystal semiconducto... | 06/24/2003 |
| 6573541 | Charge coupled device with channel well A solid-state CCD device suitable for forming into arrays and for use with suitable hardware to form video image capture devices and methods for fabricating same are provided.... | 06/03/2003 |
| 6518605 | Solid state imaging pickup device and method for manufacturing the same A solid state imaging pickup device with a single-layer electrode structure which eliminates the release area at the terminal part of the charge transfer electrodes by surrounding the charge transfer electrodes with a dummy pattern, or with a pattern form... | 02/11/2003 |
| 6441409 | Dual-line type charge transfer device A charge transfer device which comprises vertical charge transfer devices which transfer charges in the vertical direction, first and second horizontal charge transfer devices which transfer the charges from the vertical charge transfer devices in the hor... | 08/27/2002 |
| 6426238 | Charge transfer device and solid image pickup apparatus using the same A charge transfer device is provided, capable of preventing degradation of the charge transfer efficiency when the channel width becomes narrower due to the narrow channel effect. The charge transfer device of the present invention is obtained by forming ... | 07/30/2002 |
| 6420759 | Semiconductor device There is provided a semiconductor device having a new structure which allows a high reliability and a high field effect mobility to be realized in the same time. In an insulated gate transistor having an SOI structure utilizing a mono-crystal semiconducto... | 07/16/2002 |
| 6333526 | Charge transfer device and a manufacturing process therefor This invention provides a manufacturing process for a charge transfer device comprising an N-type well formed in a P-type well on a semiconductor substrate for transferring a signal charge, an N+region formed on both sides along the charge transfer direct... | 12/25/2001 |
| 6225669 | Non-uniform gate/dielectric field effect transistor A field effect transistor (FET) structure, and method for making the same, which further suppresses short-channel effects based on variations within the gate dielectric itself. The FET structure utilizes non-uniform gate dielectrics to alter the vertical ... | 05/01/2001 |
| 6207981 | Charge-coupled device with potential barrier and charge storage regions A two-phase, single-ply-electrode type charge-coupled device is provided that has a pair of a potential barrier region and a charge storage region underlying one charge transfer electrode. The charge storage region is formed in such a manner that the pote... | 03/27/2001 |
| 6187649 | Shallow trench isolation process A shallow trench isolation process is described. A pad oxide layer is formed over a substrate. A silicon nitride layer is formed over the pad oxide layer. The silicon nitride layer is patterned. The pad oxide layer and the substrate are etched using the p... | 02/13/2001 |
| 6184556 | Semiconductor device There is provided a semiconductor device having a new structure which allows a high reliability and a high field effect mobility to be realized in the same time. In an insulated gate transistor having an SOI structure utilizing a mono-crystal semiconducto... | 02/06/2001 |
| 6146953 | Fabrication method for mosfet device A fabrication method for a MOSFET device including the steps of forming a first insulating film on a semiconductor substrate wherein an active region and an isolated region are defined, forming a channel ion region by implanting impurity ions into the act... | 11/14/2000 |
| 6114718 | Solid state image sensor and its fabrication A dipping in potential well due to direct contact between transfer electrodes and metal wiring causes a drop in transfer efficiency through a CCD register. In order to eliminate or at least reduce the potential dipping, an N- -type impurity lay... | 09/05/2000 |
