Bizarre Patents
Decorative Jeweled Wheel Cover
An improved wheel is provided wherein decorative items such as gem stones are embedded in either the wheel surface, a special mounting section attached to the wheel surface, or to a spoke strap that wraps around each spoke and positions embedded gem stones on the outside surface of the spoke.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 7943969 | Transistor with a plurality of layers with different Ge concentrations A transistor and a method of fabricating the same are provided. The transistor includes a SiGe epitaxial layer formed in a recess region of a substrate at both side of a gate electrode and a SiGe capping layer formed on the SiGe epitaxial layer. The transistor furth... | 05/17/2011 |
| 7939859 | Solid state imaging device and method for manufacturing the same A solid state imaging device includes a transfer transistor for transferring signal charges generated by photoelectric conversion to a floating diffusion layer, a reset transistor for resetting a potential of the floating diffusion layer, and an amplifying transisto... | 05/10/2011 |
| 7768039 | Field effect transistors with different gate widths Four regions (a narrow NMOS region, a wide NMOS region, a wide PMOS region, and a narrow PMOS region) are defined on a semiconductor substrate. Then, after a gate insulating film and a polysilicon film are sequentially formed on the semiconductor substrate, n-type i... | 08/03/2010 |
| 7564078 | Tunable semiconductor component provided with a current barrier Semiconductor component or device is provided which includes a current barrier element and for which the impedance may be tuned (i.e. modified, changed, etc.) using a focused heating source. ... | 07/21/2009 |
| 7535038 | Solid-state imaging device and its manufacturing method A solid-state image pickup device for preventing crosstalk between adjacent pixels by providing an overflow barrier at the deep potion of a substrate. A partial P type region is provided at the predetermined position of a lower layer region of the vertical transfer ... | 05/19/2009 |
| 7479668 | Source/drain extension implant process for use with short time anneals The present invention provides, in one embodiment, a process for fabricating a metal oxide semiconductor (MOS) device (100). The process includes forming a gate (120) on a substrate (105) and forming a source/drain extension (160) in the ... | 01/20/2009 |
| 7354841 | Method for fabricating photodiode of CMOS image sensor A method for fabricating a photodiode of a CMOS image sensor is disclosed, to improve a charge accumulation capacity in the photodiode, which includes the steps of defining a semiconductor substrate as an active area and a field area by forming an STI layer; firstly... | 04/08/2008 |
| 7351598 | Solid-stage image pickup device and method for producing the same A solid-state image pickup device includes an element isolation insulating film electrically isolating pixels on the surface of a well region; a first isolation diffusion layer electrically isolating the pixels under the element isolation insulating film; and a seco... | 04/01/2008 |
| 7339235 | Semiconductor device having SOI structure and manufacturing method thereof A fine semiconductor device having a short channel length while suppressing a short channel effect. Linearly patterned or dot-patterned impurity regions 104 are formed in a channel forming region 103 so as to be generally parallel with the channel dire... | 03/04/2008 |
| 7301183 | Organic field-effect transistor and method of making same based on polymerizable self-assembled monolayers An organic field-effect transistor and a method of making the same include a self-assembled monolayer (SAM) of bifunctional molecules disposed between a pair of electrodes as a channel material. The pair of electrodes and the SAM of bifunctional molecules are formed... | 11/27/2007 |
| 7247890 | Semiconductor device and manufacturing method thereof Disclosed is herein a semiconductor device having a DRAM with less scattering of threshold voltage of MISFET in a memory cell and having good charge retainability of a capacitor, and a manufacturing method of the semiconductor device. An anti-oxidation film is forme... | 07/24/2007 |
| 7217989 | Composition for selectively polishing silicon nitride layer and polishing method employing it To provide a polishing composition whereby the stock removal rate of a silicon nitride layer is higher than the stock removal rate of a silicon oxide layer, there is substantially no adverse effect against polishing planarization, and a sufficient stock removal rate... | 05/15/2007 |
| 7211458 | Methods of fabricating strained semiconductor-on-insulator field-effect transistors and related devices A method of fabricating a semiconductor device includes forming a strained first semiconductor layer on an insulating layer that is between second semiconductor layers. The strained first semiconductor layer may be epitaxially grown from the second semiconductor lay... | 05/01/2007 |
| 7176527 | Semiconductor device and method of fabricating same A semiconductor device and a method of fabricating the same suppress a substrate floating effect without causing lowering of a degree of integration. The semiconductor device has a Silicon-On-Insulator structure which includes a semiconductor layer formed on an insu... | 02/13/2007 |
| 7157754 | Solid-state imaging device and interline transfer CCD image sensor A high-performance solid-state imaging device is provided. The solid-state imaging device includes: a plurality of pixel cells; and a driving unit. Each of the plurality of pixel cells includes: a photodiode that converts incident light into a signal charge and stor... | 01/02/2007 |
| 7154136 | Isolation structures for preventing photons and carriers from reaching active areas and methods of formation Regions of an integrated circuit are isolated by a structure that includes at least one isolating trench on the periphery of an active area. The trench is deep, extending at least about 0.5 μm into the substrate. The isolating structure prevents photons and electro... | 12/26/2006 |
| 7116583 | Electrically programmable memory cell and methods for programming and reading from such a memory cell The invention relates to an electrically programmable memory cell comprising a memory transistor having a source and a drain zone and also a storage electrode and a control electrode, and a selection transistor having a source and a drain zone and also a control ele... | 10/03/2006 |
| 7084441 | Semiconductor devices having a hybrid channel layer, current aperture transistors and methods of fabricating same Transistors and/or methods of fabricating transistors that include a source contact, drain contact and gate contact are provided. In some embodiments, a channel region is provided between the source and drain contacts and at least a portion of the channel regions in... | 08/01/2006 |
| 7075128 | Charge transfer element having high output sensitivity A charge transfer element comprising a reverse conductive type well formed on the surface of one conductive type semiconductor substrate, the one conductive type channel region extending in one direction relative to the well, a transfer electrode formed intersecting... | 07/11/2006 |
| 7064421 | Wire bonding package A wire bonding package has a housing having a plurality of pins, a circuit board installed inside the housing and having at least a trace connected to a pin of the housing, at least a die installed on the circuit board and having a plurality of bonding pads, and at ... | 06/20/2006 |
| 7064476 | Emitter Electron emitters and a method of fabricating emitters are disclosed, having a concentration gradient of impurities, such that the highest concentration of impurities is at the apex of the emitters and decreases toward the base of the emitters. The method comprises ... | 06/20/2006 |
| 7037814 | Single mask control of doping levels In an integrated circuit, dopant concentration levels are adjusted by making use of a perforated mask. Doping levels for different regions across an integrated circuit can be differently defined by making use of varying size and spacings to the perforations in the m... | 05/02/2006 |
| 7038258 | Semiconductor device having a localized halo implant therein and method of manufacture therefor The present invention provides a semiconductor device 200 having a localized halo implant 250 located therein, a method of manufacture therefore and an integrated circuit including the semiconductor device. In one embodiment, the semiconductor device | 05/02/2006 |
| 7023482 | Processing apparatus In order to suppress variations in the set currents of a plurality of constant current circuits, there is provided a processing apparatus having a constant current supply unit including a plurality of constant current circuits, a plurality of sample/hold circuits fo... | 04/04/2006 |
| 6992279 | Method for adjusting a multi-beam source unit A method for adjusting a multi-beam source unit including a multi-beam laser diode provided with light emitting points, and a collimator lens includes measuring a state of a position of the light emitting points with respect to a standard design line based on beam s... | 01/31/2006 |
| 6974742 | Method for fabricating complementary metal oxide semiconductor image sensor The present invention relates to a method for fabricating a complementary metal oxide semiconductor (CMOS) image sensor, wherein a mini-p-well is stably formed in a pixel region being correspondent to a trend of large scale of integration. The method includes the st... | 12/13/2005 |
| 6949777 | Method of controlling insulated gate transistor An insulated gate transistor is comprised of a semiconductor thin film, a first gate insulating film formed on a main surface of the semiconductor thin film, a first conductive gate formed on the first gate insulating film, first and second confronting semiconductor... | 09/27/2005 |
| 6914270 | IGBT with PN insulation and production method The IGBT (insulated gate bipolar transistor) has a weakly doped drift zone of a first conductivity formed in a weakly doped semiconductor substrate of the same conductivity. A highly doped first well zone of the first conductivity and a highly doped second well zone... | 07/05/2005 |
| 6909976 | Method for calculating threshold voltage of pocket implant MOSFET A threshold voltage model with an impurity concentration profile in a channel direction taken into account is provided in the pocket implant MOSFET. With penetration length of the implanted pocket in the channel direction and the maximum impurity concentration of th... | 06/21/2005 |
| 6878977 | Photoelectric conversion device, and image sensor and image input system making use of the same In a photoelectric conversion device comprising a first-conductivity type first semiconductor region located in a pixel region, a second-conductivity type second semiconductor region provided in the first semiconductor region, and a wiring for electrically connectin... | 04/12/2005 |
| 6847065 | Radiation-hardened transistor fabricated by modified CMOS process An NMOS field effect transistor (1) is made radiation hard by a pair of guard band implants (115) of limited horizontal extent, extending between the source (30A) and drain (30B) along the edge of the transistor body, and extending only t... | 01/25/2005 |
| 6744083 | Submicron MOSFET having asymmetric channel profile A MOSFET semiconductor device having an asymmetric channel region between the source region and the drain region. In one embodiment, the device comprises a mesa structure on a silicon substrate with the source region being in the substrate and the mesa structure ext... | 06/01/2004 |
| 6642558 | Method and apparatus of terminating a high voltage solid state device Termination of a high voltage device is achieved by a plurality of discrete deposits of charge that are deposited in varying volumes and/or spacing laterally along a termination region. The manner in which the volumes and/or spacing varies also varies bet... | 11/04/2003 |
| 6639259 | Charge-coupled device The invention relates to a CCD of the buried-channel type comprising a charge-transport channel in the form of a zone (12) of the first conductivity type, for example the n-type, in a well (13) of the opposite conductivity type, in the example the p-type.... | 10/28/2003 |
| 6583474 | Semiconductor device There is provided a semiconductor device having a new structure which allows a high reliability and a high field effect mobility to be realized in the same time. In an insulated gate transistor having an SOI structure utilizing a mono-crystal semiconducto... | 06/24/2003 |
| 6545302 | Image sensor capable of decreasing leakage current between diodes and method for fabricating the same An image sensor capable of preventing the degradation of pinned photodiodes and the generation of leakage current between neighboring pinned photodiodes is provided. The disclosed image sensor contains a plurality of pixel units, each pixel unit having a ... | 04/08/2003 |
| 6541804 | Junction-isolated lateral MOSFET for high-/low-side switches The junction insulated lateral MOSFET is suitable for high/low side switches. A p-conductive wall between an n-conductive source zone and an n-conductive drain zone, together with the source zone and drain zone, extend to an n-conductive substrate. The so... | 04/01/2003 |
| 6534822 | Silicon on insulator field effect transistor with a double Schottky gate structure A field effect transistor (FET) is formed on a silicon on insulator (SOI) substrate in the thin silicon layer above the insulating buried oxide layer. The channel region is lightly doped with an impurity to increase free carrier conductivity. The source r... | 03/18/2003 |
| 6479846 | Metal oxide semiconductor field effect transistor having a relatively high doped region in the channel for improved linearity A field effect transistor is disclosed having a relatively high doped region (of the same type dopant as the channel) to reduce the change in the depletion region within the channel with changes in the drain voltage (Vd). Changes in the drain current (Id)... | 11/12/2002 |
| 6420759 | Semiconductor device There is provided a semiconductor device having a new structure which allows a high reliability and a high field effect mobility to be realized in the same time. In an insulated gate transistor having an SOI structure utilizing a mono-crystal semiconducto... | 07/16/2002 |
