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| Number | Title | Issue Date |
| 7414279 | Semiconductor device with improved overlay margin and method of manufacturing the same Semiconductor devices with an improved overlay margin and methods of manufacturing the same are provided. In one aspect, a method includes forming a buried bit line in a substrate; forming an isolation layer in the substrate to define an active region, the isolation... | 08/19/2008 |
| 7365378 | MOSFET structure with ultra-low K spacer A MOSFET structure and method of fabricating the structure incorporates a multi-layer sidewall spacer to suppress parasitic overlap capacitance between the gate conductor and the source/drain extensions without degrading drive current and, thereby, effecting overall... | 04/29/2008 |
| 7358550 | Field effect transistor An field effect transistor includes a first semiconductor region, a gate electrode insulatively disposed over the first semiconductor region, source and drain electrodes between which the first semiconductor region is sandwiched, and second semiconductor regions eac... | 04/15/2008 |
| 7351661 | Semiconductor device having trench isolation layer and a method of forming the same A semiconductor device having a trench isolation layer in a semiconductor substrate is provided, wherein the trench isolation layer includes a silicon nitride liner, a silicon oxide liner; and a buried layer, wherein the buried layer includes a first buried layer fo... | 04/01/2008 |
| 7310268 | Float gate memory device A float gate memory device comprises a bottom word line, a float channel layer formed on the bottom word line and kept at a floating state, a float gate, and a top word line formed on the float gate in parallel with the bottom word line. In the float gate formed on ... | 12/18/2007 |
| 7301804 | NROM memory cell, memory array, related devices and methods An array of memory cells configured to store at least one bit per one F2 includes substantially vertical structures providing an electronic memory function spaced apart a distance equal to one half of a minimum pitch of the array. The structures providing... | 11/27/2007 |
| 7238993 | CMOS pixel with dual gate PMOS A pixel circuit with a dual gate PMOS is formed by forming two P+ regions in an N− well. The N− well is in a P− type substrate. The two P+ regions form the source and drain of a PMOS transistor. The PMOS t... | 07/03/2007 |
| 7230296 | Self-aligned low-k gate cap A CMOS structure in which the gate-to-drain/source capacitance is reduced as well as various methods of fabricating such a structure are provided. In accordance with the present invention, it has been discovered that the gate-to-drain/source capacitance can be signi... | 06/12/2007 |
| 7220683 | Transparent amorphous carbon structure in semiconductor devices A transparent amorphous carbon layer is formed. The transparent amorphous carbon layer has a low absorption coefficient such that the amorphous carbon is transparent in visible light. The transparent amorphous carbon layer may be used in semiconductor devices for di... | 05/22/2007 |
| 7192829 | Methods of forming floating gate transistors Floating gate transistors and methods of forming the same are described. In one implementation, a floating gate is formed over a substrate. The floating gate has an inner first portion and an outer second portion. Conductivity enhancing impurity is provided in the i... | 03/20/2007 |
| 7173294 | Image sensor with reduced sensitivity to gamma rays The CCD image sensor addresses the problem of noise, due to background charge generated by Compton scattering of gamma rays. In applications, in which an imager must operate in a high-radiation environment, such background noise reduces the video signal/noise. This ... | 02/06/2007 |
| 7173274 | Incorporation of carbon in silicon/silicon germanium epitaxial layer to enhance yield for Si-Ge bipolar technology A SiGe bipolar transistor containing substantially no dislocation defects present between the emitter and collector region and a method of forming the same are provided. The SiGe bipolar transistor includes a collector region of a first conductivity type; a SiGe bas... | 02/06/2007 |
| 7148543 | Semiconductor chip which combines bulk and SOI regions and separates same with plural isolation regions A semiconductor chip includes a base substrate, a bulk device region having a bulk growth layer on a part of the base substrate, an SOI device region having a buried insulator on the base substrate and a silicon layer on the buried insulator, and a boundary layer lo... | 12/12/2006 |
| 7138671 | Solid-state image sensor with photoelectric conversion units each having a first conductive-type impurity region boundary non-coplanar with second conductive-type impurity region boundaries A first p+-type region on a surface of a photodiode unit is formed over a region from a surface of the photodiode unit through a surface of a signal charge read-out unit until reaching the charge transfer unit. Also, the following structure is adapted: th... | 11/21/2006 |
| 7132702 | Image sensor In the present invention, a charge transfer unit is arranged on a first-plane side of a thinly-formed semiconductor base. Charge accumulating units are arranged on a second-plane side, the opposite side. A depletion prevention layer is arranged closer to the second-... | 11/07/2006 |
| 7132201 | Transparent amorphous carbon structure in semiconductor devices A transparent amorphous carbon layer is formed. The transparent amorphous carbon layer has a low absorption coefficient such that the amorphous carbon is transparent in visible light. The transparent amorphous carbon layer may be used in semiconductor devices for di... | 11/07/2006 |
| 7098512 | Layout patterns for deep well region to facilitate routing body-bias voltage Layout patterns for the deep well region to facilitate routing the body-bias voltage in a semiconductor device are provided and described. The layout patterns include a diagonal sub-surface mesh structure, an axial sub-surface mesh structure, a diagonal sub-surface ... | 08/29/2006 |
| 7095440 | Photodiode-type pixel for global electronic shutter and reduced lag Operation for global electronic shutter photodiode-type pixels. In a first mode of operation, lag is reduced through global reset of the photodiode array and fixed pattern noise is eliminated through comparison of the photosignal level and the reset level of the flo... | 08/22/2006 |
| 7091530 | High-speed, high-sensitivity charge-coupled device with independent pixel control of charge collection and storage A charge-coupled device imager including an array of super pixels disposed in a semiconductor substrate having a surface that is accessible to incident illumination. For each super pixel there is provided a plurality of subpixels which each correspond to one in the ... | 08/15/2006 |
| 7087182 | Process of forming an electrically erasable programmable read only memory with an oxide layer exposed to hydrogen and nitrogen The present invention provides a flash memory integrated circuit and a method of fabricating the same. A tunnel dielectric in an erasable programmable read only memory (EPROM) device is nitrided with a hydrogen-bearing compound, particularly ammonia. Hydrogen is thu... | 08/08/2006 |
| 7057302 | Static random access memory A static random access memory has first and second complementary field-effect transistors. The first complementary field-effect transistor includes a semiconductor substrate, a first field-effect transistor of electron conduction type which has a first drain region ... | 06/06/2006 |
| 7056795 | Thin-film transistor used as heating element for microreaction chamber The thin film transistor formed of polycrystalline silicon is positioned adjacent a heat reaction chamber. The gate electrode for the transistor is formed within a silicon substrate and a gate dielectric is positioned over the gate electrode. A pass transistor is co... | 06/06/2006 |
| 7027093 | Method of transferring electric charge from image sensing device and image sensing device An image sensing device for transferring electric charge from a plurality of photoelectric converters disposed therein. The image sensing device is divided into a plurality of pixel areas. At least a pair of the divided pixel areas contiguous to each other have a ve... | 04/11/2006 |
| 6936898 | Diagonal deep well region for routing body-bias voltage for MOSFETS in surface well regions Diagonal deep well region for routing the body-bias voltage for MOSFETS in surface well regions is provided and described. ... | 08/30/2005 |
| 6928335 | Device for optimizing fabrics based on measured thread data and optimization method An apparatus for optimizing actual woven fabrics on the basis of measured yarn data has at least one measuring device for measuring the yarn diameter, a structure input device for inputting and freely changing definable structures, a device for controlling the measu... | 08/09/2005 |
| 6917041 | Event-driven charge-coupled device design and applications therefor An event-driven X-ray CCD imager device uses a floating-gate amplifier or other non-destructive readout device to non-destructively sense a charge level in a charge packet associated with a pixel. The output of the floating-gate amplifier is used to identify each pi... | 07/12/2005 |
| 6909126 | Imager cell with pinned transfer gate An imager cell includes a photoreceptor, a sense node, and a pinned transfer gate. The pinned transfer gate is tied to the same potential of a substrate of the imager cell and is disposed between the photoreceptor and the sense node in order to transfer charge betwe... | 06/21/2005 |
| 6909154 | Sacrificial annealing layer for a semiconductor device and a method of fabrication Numerous embodiments of a method and apparatus for a sacrificial annealing layer are disclosed. In one embodiment, a method of forming a sacrificial annealing layer for a semiconductor device comprises forming one or more sacrificial layers on at least a portion of ... | 06/21/2005 |
| 6780666 | Imager photo diode capacitor structure with reduced process variation sensitivity A pixel cell having two capacitors connected in series where each capacitor has a capacitance approximating that at of the periphery capacitors and such that the effective capacitance of the series capacitors is smaller than that of each of the periphery capacitors.... | 08/24/2004 |
| 6777725 | NROM memory circuit with recessed bitline An integrated memory circuit of the type of an NROM memory includes recessed bit lines formed of a material having a low ohmic resistance. By recessing the bit lines with respect to the semiconductor substrate surface of a peripheral controlling circuit for an array... | 08/17/2004 |
| 6734475 | Charge pump device P type well regions 31 and 32 are formed in N type well regions 21 and 22 respectively. The N type well regions 21 and 22 are formed separately each other. Charge transfer MOS transistors M2 and M3 are formed i... | 05/11/2004 |
| 6486489 | Transistor There is provided a transistor, which includes a deoxyribonucleic acid molecule or a deoxyribonucleic acid molecule aggregate as a part of structural materials, has a source electrode member, a drain electrode member and a gate electrode member, in which ... | 11/26/2002 |
| 6465820 | CMOS compatible single phase CCD charge transfer device A single phase charge-couple device (CCD) transfer device in a substrate of a first conductivity type. The device includes a gated region and a photo-diode region. The gated region includes a gated part and a gate electrode insulatively spaced over the ga... | 10/15/2002 |
| 6448613 | Fabrication of a field effect transistor with minimized parasitic Miller capacitance A field effect transistor is fabricated to have a drain overlap and a source overlap to minimize series resistance between the gate and the drain and between the gate and the source of the field effect transistor. The parasitic Miller capacitance formed b... | 09/10/2002 |
| 6376868 | Multi-layered gate for a CMOS imager A multi-layered gate for use in a CMOS or CCD imager formed with a second gate at least partially overlapping it. The multi-layered gate is a complete gate stack having an insulating layer, a conductive layer, an optional silicide layer, and a second insu... | 04/23/2002 |
| 6369413 | Split-gate virtual-phase CCD image sensor with a diffused lateral overflow anti-blooming drain structure and process of making Generally, and in one form of the invention, a monolithic solid state image-sensing device is disclosed. The device utilizes only a single layer of polysilicon deposition in its fabrication process that is split into two or more phases by very narrow gaps... | 04/09/2002 |
| 6355949 | Solid state imaging apparatus with horizontal charge transfer register which can transfer signal charge faster A charge transfer structure includes an insulating film on a first semiconductor region, a plurality of transfer electrodes and a signal generating circuit. The plurality of transfer electrodes are formed on the insulating film, and each of the plurality ... | 03/12/2002 |
| 6194748 | MOSFET with suppressed gate-edge fringing field effect A method of fabricating an integrated circuit with less susceptibility to gate-edge fringing field effect is disclosed. The transistor includes a low-k dielectric spacer and a high-k gate dielectric. The high-k gate dielectric can be tantalum pentaoxide o... | 02/27/2001 |
| 5978026 | Solid-state image pickup device A solid-state image pickup device of the charge-coupled type is improved in that the width W1 (as viewed in the charge transfer direction) of each of the transfer gate electrodes for generating transfer elements in the field shift mode, the width W2 (as v... | 11/02/1999 |
| 5900654 | Radiation hardened charge coupled device A structure and method is described for fabricating a nuclear radiation induced damage resistant P-type buried channel charge-coupled device (P-BCD) which converts an optical image focused thereon into a time varying electrical signal. The invention uses ... | 05/04/1999 |
