Safety System For Remove a Rider From a Vehicle by Deploying a Parachute
Methods and apparatus for reducing the velocity of a rider in or on an open cockpit vehicle when the rider is thrown from the vehicle.
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| Number | Title | Issue Date |
| 8188518 | Thin film transistor structure of pixel with drain extensions overlapping gate electrode and gate electrode extention A thin film transistor structure of a pixel is provided. In the present invention, a first metal layer serves as a gate electrode, and the gate electrode includes an extending gate electrode portion. A second metal layer includes a drain electrode partially and resp... | 05/29/2012 |
| 8178910 | Semiconductor device The semiconductor device according to the present invention includes an SJMOSFET having a plurality of base regions formed at an interval from each other and an SBD (Schottky Barrier Diode) having a Schottky junction between the plurality of base regions. The SBD is... | 05/15/2012 |
| 8174054 | Field effect transistor with interdigitated fingers and method of manufacturing thereof A field effect transistor comprising a semiconductor substrate comprising an electrically conducting channel layer therein; a plurality of source and drain fingers on a first face of the substrate, each finger separated from the adjacent finger by a gate channel; th... | 05/08/2012 |
| 8174055 | Formation of FinFET gate spacer Gate spacers are formed in FinFETS having a bottom portion of a first material extending to the height of the fins, and a top portion of a second material extending above the fins. An embodiment includes forming a fin structure on a substrate, the fin structure havi... | 05/08/2012 |
| 8174053 | Semiconductor device, production method thereof, and electronic device The present invention provides a semiconductor device which includes a thin film transistor as a resistance element, wherein a variation in resistance of the thin film transistor is suppressed without increasing an area of the resistance element and the resistance e... | 05/08/2012 |
| 8138526 | Semiconductor structures including dual fins Fin-FET (fin field effect transistor) devices and methods of fabrication are disclosed. The Fin-FET devices include dual fin structures that may form a channel region between a source region and a drain region. In some embodiments, the dual fin structures are formed... | 03/20/2012 |
| 8084788 | Method of forming source and drain of a field-effect-transistor and structure thereof A semiconductor fabrication method involving the use of eSiGe is disclosed. The eSiGe approach is useful for applying the desired stresses to the channel region of a field effect transistor, but also can introduce complications into the semiconductor fabrication pro... | 12/27/2011 |
| 8076701 | Large scale patterned growth of aligned one-dimensional nanostructures A method of making nanostructures using a self-assembled monolayer of organic spheres is disclosed. The nanostructures include bowl-shaped structures and patterned elongated nanostructures. A bowl-shaped nanostructure with a nanorod grown from a conductive substrate... | 12/13/2011 |
| 8063418 | Semiconductor device In a high-voltage semiconductor switching element, in addition to a first emitter region that is necessary for switching operations, a second emitter region, which is electrically connected with the first emitter region through a detection resistor in current detect... | 11/22/2011 |
| 8035136 | Semiconductor device and method of manufacturing the same In a semiconductor device and a method of manufacturing the same, a substrate is defined into active and non-active regions by a device isolation layer and a recessed portion is formed on the active region. A gate electrode includes a gate insulation layer on an inn... | 10/11/2011 |
| 8004018 | Fabrication method of electronic devices based on aligned high aspect ratio nanoparticle networks A layer of high aspect ratio nanoparticles is disposed on a surface of a substrate under the influence of an electrical field applied on the substrate. To create the electrical field, a voltage is applied between a pair of electrodes arranged near the substrate or o... | 08/23/2011 |
| 7999290 | Dual panel type organic electroluminescent device and method of fabricating the same An organic electroluminescent device includes first and second substrates facing each other and spaced apart from each other; a gate line on an inner surface of the first substrate; a data line and a power line crossing the gate line and spaced apart from each other... | 08/16/2011 |
| 7982246 | Selection transistor Provided are a selection transistor and a method of fabricating the same. A selection transistor can be formed on an active region in a semiconductor substrate to include a gate electrode that includes recessed portions of a sidewall of the gate electrode which are ... | 07/19/2011 |
| 7984408 | Structures incorporating semiconductor device structures with reduced junction capacitance and drain induced barrier lowering Design structure embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes semiconductor device structures characterized by reduced junction capacitance and drain induced barrier lowering. The semiconducto... | 07/19/2011 |
| 7964897 | Direct contact to area efficient body tie process flow A process flow for fabricating shallow trench isolation (STI) devices with direct body tie contacts is provided. The process flow follows steps similar to standard STI fabrication methods except that in one of the etching steps, body tie contacts are etched through ... | 06/21/2011 |
| 7956386 | Wiring structure in a semiconductor device, method of forming the wiring structure, semiconductor device including the wiring structure and method of manufacturing the semiconductor device A wiring structure in a semiconductor device may include a first insulation layer formed on a substrate, a first contact plug, a capping layer pattern, a second insulation layer and a second contact plug. The first insulation layer has a first opening that exposes a... | 06/07/2011 |
| 7937675 | Structure including transistor having gate and body in direct self-aligned contact A design structure including a transistor having a directly contacting gate and body is disclosed. In one embodiment, the transistor includes a gate; a body; and a dielectric layer extending over the body to insulate the gate from the body along an entire surface of... | 05/03/2011 |
| 7884396 | Method and structure for self-aligned device contacts Disclosed are embodiments of a semiconductor structure with a partially self-aligned contact in lower portion of the contact is enlarged to reduce resistance without impacting device yield. Additionally, the structure optionally incorporates a thick middle-of-the-li... | 02/08/2011 |
| 7868360 | Semiconductor device with heat-resistant gate There are disclosed TFTs that have excellent characteristics and can be fabricated with a high yield. The TFTs are fabricated, using an active layer crystallized by making use of nickel. Gate electrodes are comprising tantalum. Phosphorus is introduced into source/d... | 01/11/2011 |
| 7859026 | Vertical semiconductor device A semiconductor device and methods for its fabrication are provided. The semiconductor device comprises a trench formed in the semiconductor substrate and bounded by a trench wall extending from the semiconductor surface to a trench bottom. A drain region and a sour... | 12/28/2010 |
| 7855403 | Hybrid carbon nanotube FET (CNFET)-FET static RAM (SRAM) and method of making same Hybrid carbon nanotube FET (CNFET), static ram (SRAM) and method of making same. A static ram memory cell has two cross-coupled semiconductor-type field effect transistors (FETs) and two nanotube FETs (NTFETs), each having a channel region made of at least one semic... | 12/21/2010 |
| 7847322 | Semiconductor memory device and method of manufacturing the same This disclosure concerns a semiconductor memory device comprising a semiconductor substrate; a first dielectric film provided on the semiconductor substrate; two Fins provided on the first dielectric film and made of a semiconductor material; a second dielectric fil... | 12/07/2010 |
| 7847321 | Semiconductor device and manufacturing method thereof A semiconductor device includes a field effect transistor and a strain generating layer to apply a stress to a channel region of the field effect transistor. The strain generating layer contains at least one of oxygen and nitrogen of 1.0×1018 cm−3... | 12/07/2010 |
| 7842977 | Gate electrode structure, MOS field effect transistors and methods of manufacturing the same A gate electrode structure comprises at least one bi-layer, wherein each bi-layer comprises a plating film and a stress amplifier film. The plating film includes a poly-crystalline material. The stress amplifier film determines the crystallization result of the poly... | 11/30/2010 |
| 7816709 | Single-walled carbon nanotube-ceramic composites and methods of use Composites of single-walled carbon nanotubes (SWNTs) and a ceramic support (e.g., silica) comprising a small amount of catalytic metal, e.g., cobalt and molybdenum, are described. The particle comprising the metal and ceramic support is used as the catalyst for the ... | 10/19/2010 |
| 7812376 | Nanotube based nonvolatile memory device and a method of fabricating and operating the same Provided are a nonvolatile memory device and methods of fabricating and operating the same. The memory device may include a substrate, at least a first and a second electrode on the substrate to be spaced a distance from each other, a conductive nanotube between the... | 10/12/2010 |
| 7804112 | Semiconductor device The semiconductor device according to the present invention includes an SJMOSFET having a plurality of base regions formed at an interval from each other and an SBD (Schottky Barrier Diode) having a Schottky junction between the plurality of base regions. The SBD is... | 09/28/2010 |
| 7800141 | Electronic device including a semiconductor fin An electronic device can include a semiconductor fin overlying an insulating layer. The electronic device can also include a semiconductor layer overlying the semiconductor fin. The semiconductor layer can have a first portion and a second portion that are spaced-ap... | 09/21/2010 |
| 7800140 | Semiconductor integrated circuit A semiconductor integrated circuit is provided which entails no increase in the correction time of OPC and in which non-uniformity in the gate lengths due to the optical proximity effects is surely suppressed. A plurality of standard cells (C1, C2, C | 09/21/2010 |
| 7800139 | Thin film transistor and method for fabricating the same, and liquid crystal display device and method for manufacturing the same A thin film transistor (TFT) including a nanowire semiconductor layer having nanowires aligned in one direction in a channel region is disclosed. The nanowire semiconductor layer is selectively formed in the channel region. A method for fabricating the TFT, a liquid... | 09/21/2010 |
| 7795647 | Curled semiconductor transistor A curled transistor comprises a coiled semiconductor substrate having a plurality of concentrically curled layers. Source and drain regions are configured on a portion of the coiled semiconductor substrate, and a gate dielectric is positioned between the source and ... | 09/14/2010 |
| 7795648 | Semiconductor device comprising capacitor and method of fabricating the same A semiconductor device, having a memory cell region and a peripheral circuit region, includes an insulating film, having an upper surface, formed on a major surface of a semiconductor substrate to extend from the memory cell region to the peripheral circuit region. ... | 09/14/2010 |
| 7791112 | Channel stress engineering using localized ion implantation induced gate electrode volumetric change A method for fabricating a semiconductor structure uses a volumetric change ion implanted into a volumetric change portion of a gate electrode that is located over a channel region within a semiconductor substrate to form a volume changed portion of the gate electro... | 09/07/2010 |
| 7786514 | Switching device for a pixel electrode The invention discloses a switching device for a pixel electrode of display device. The switching device comprises a gate formed on a substrate; a gate-insulating layer formed on the gate; a first buffer layer formed between the substrate and the gate and/or between... | 08/31/2010 |
| 7777256 | Mask ROM device, semiconductor device including the mask ROM device, and methods of fabricating mask ROM device and semiconductor device A mask read-only memory (ROM) device, which can stably output data, includes an on-cell and an off-cell. The on-cell includes an on-cell gate structure on a substrate and an on-cell junction structure within the substrate. The off-cell includes an off-cell gate stru... | 08/17/2010 |
| 7745856 | Lipid nanotube or nanowire sensor A sensor apparatus comprising a nanotube or nanowire, a lipid bilayer around the nanotube or nanowire, and a sensing element connected to the lipid bilayer. Also a biosensor apparatus comprising a gate electrode; a source electrode; a drain electrode; a nanotube or ... | 06/29/2010 |
| 7732840 | Semiconductor device A second-conductivity-type transistor includes a source and drain formed by a second-conductivity-type diffusion layer formed on a first-conductivity-type semiconductor layer; and a gate formed on the first-conductivity-type semiconductor layer sandwiched between th... | 06/08/2010 |
| 7723756 | Silicon pillars for vertical transistors In order to form a more stable silicon pillar which can be used for the formation of vertical transistors in DRAM cells, a multi-step masking process is used. In a preferred embodiment, an oxide layer and a nitride layer are used as masks to define trenches, pillars... | 05/25/2010 |
| 7719032 | Electronic device and its manufacturing method A microelectronic device and a method for producing the device can overcome the disadvantages of known electronic devices composed of carbon molecules, and can deliver performance superior to the known devices. An insulated-gate field-effect transistor includes a mu... | 05/18/2010 |
| 7719035 | Low contact resistance CMOS circuits and methods for their fabrication A low contact resistance CMOS integrated circuit and method for its fabrication are provided. The CMOS integrated circuit comprises a first transition metal electrically coupled to the N-type circuit regions and a second transition metal different than the first tra... | 05/18/2010 |