Bizarre Patents
Cloaking System Using Optoelectronically Controlled Camouflage
A Cloaking System designed to operate in the visible light spectrum, utilizes optoelectronics and/or photonic components to conceal an object within it.
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| Number | Title | Issue Date |
| 8188517 | Three-dimensional nonvolatile memory device and method for fabricating the same A three-dimensional nonvolatile memory device includes: a plurality of channel structures extending in parallel in a first direction and comprising a plurality of channel layers that are alternatively stacked with a plurality of interlayer insulating layers over a s... | 05/29/2012 |
| 8183602 | Nonvolatile semiconductor memory device including via-holes continuously formed through plural cell array layers A nonvolatile semiconductor memory device comprises a semiconductor substrate; a cell array block formed on the semiconductor substrate and including plural stacked cell array layers each with a plurality of first lines, a plurality of second lines crossing the plur... | 05/22/2012 |
| 8178908 | Electrical contact structure having multiple metal interconnect levels staggering one another An electrical contact structure distributes current along a length thereof. The electrical contact structure includes a plurality of n metal rectangles on n levels of metal. The rectangle on one metal level is at least as wide in width and vertically covers in width... | 05/15/2012 |
| 8178909 | Integrated circuit cell architecture configurable for memory or logic elements An improved integrated circuit cell architecture is provided for configurability between a memory cell or logic elements. The cell architecture is configured on variable layers above a first layer of metal, with the first layer of metal and layers therebelow reserve... | 05/15/2012 |
| 8178907 | Nanoscopic wire-based electrical crossbar memory-devices and arrays Electrical devices comprised of nanoscopic wires are described, along with methods of their manufacture and use. The nanoscopic wires can be nanotubes, preferably single-walled carbon nanotubes. They can be arranged in crossbar arrays using chemically patterned surf... | 05/15/2012 |
| 8134187 | Integrated mask-programmable logic devices with multiple metal levels and manufacturing process thereof Integrated mask-programmable device, having a plurality of metal levels including a top metal level, a bottom metal level and a first intermediate metal level formed between the top and bottom metal levels, and a plurality of via levels arranged between the bottom a... | 03/13/2012 |
| 8120068 | Three-dimensional memory structures having shared pillar memory cells A three-dimensional non-volatile memory system is disclosed including a memory array utilizing shared pillar structures for memory cell formation. A shared pillar structure includes two non-volatile storage elements. A first end surface of each pillar contacts one a... | 02/21/2012 |
| 8097903 | Semiconductor memory device A semiconductor memory device comprises a semiconductor substrate; a memory block formed on the semiconductor substrate and including plural stacked cell array layers of cell arrays each comprising a plurality of first lines, a plurality of second lines crossing the... | 01/17/2012 |
| 8053814 | On-chip embedded thermal antenna for chip cooling An apparatus comprises a first layer within a semiconductor chip having active structures electrically connected to other active structures and having electrically isolated first inactive structures. A second layer within the semiconductor chip is physically connect... | 11/08/2011 |
| 8022442 | Semiconductor device having STI with nitride liner and UV light shielding film A semiconductor device has: a silicon substrate; trench formed downward from the surface of the silicon substrate, the trench defining active regions on the surface of the silicon substrate; a first liner layer of a silicon nitride film covering an inner wall of the... | 09/20/2011 |
| 8022443 | Memory and interconnect design in fine pitch An integrated circuit includes a plurality of signal lines. A first signal line layer includes a plurality of first signal lines. A second signal line layer includes a plurality of second signal lines arranged on top of and insulated from the first signal line layer... | 09/20/2011 |
| 8013364 | Semiconductor devices and structures thereof A structure having air gaps between interconnects is disclosed. A first insulating material is deposited over a workpiece, and a second insulating material having a sacrificial portion is deposited over the first insulating material. Conductive lines are formed in t... | 09/06/2011 |
| 8004017 | Buried circumferential electrode microcavity plasma device arrays, electrical interconnects, and formation method A preferred embodiment microcavity plasma device array of the invention includes a plurality of first metal circumferential metal electrodes that surround microcavities in the device. The first circumferential electrodes are buried in a metal oxide layer and surroun... | 08/23/2011 |
| 7994545 | Methods, structures, and designs for self-aligning local interconnects used in integrated circuits Methods, structures and designs for self-aligned local interconnects are provided. The method includes designing diffusion regions to be in a substrate. Some of a plurality of gates are designed to be active gates and some of the plurality of gates are designed to b... | 08/09/2011 |
| 7989850 | Array substrate and method of fabricating the same An array substrate includes first and second gate electrodes on a substrate; a gate insulating layer on the first and second gate electrodes; first and second active layers on the gate insulating layer; an interlayer insulating layer on the first and second active l... | 08/02/2011 |
| 7952120 | Semiconductor device Provided are embodiments of a semiconductor device having bit lines and bit bar lines. The bit lines and the bit bar lines are arranged in alternate succession across a substrate. At least two of proximate bit lines, bit line bars, power lines, and ground lines of t... | 05/31/2011 |
| 7928476 | Semiconductor device and method of manufacturing the same A semiconductor device has a first insulating film formed over a semiconductor substrate, a first opening formed in the first insulating film, a first manganese oxide film formed along an inner wall of the first opening, a first copper wiring embedded in the first o... | 04/19/2011 |
| 7898007 | Semiconductor devices including line patterns separated by cutting regions Semiconductor devices are provided. A semiconductor device can include a substrate and a plurality of dummy line patterns on the substrate that extend in a first direction parallel with one another. Each of the dummy line patterns can include a plurality of sub-line... | 03/01/2011 |
| 7895559 | Method for designing structured ASICs in silicon processes with three unique masking steps A multi-function core base cell includes a set of functional microcircuits. These microcircuits are used to design a Library of Logic Function Macros. The functional macros consisting of one or more microcircuits have a fixed and complete physical layout similar to ... | 02/22/2011 |
| 7888707 | Gated diode nonvolatile memory process A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of... | 02/15/2011 |
| 7863654 | Top layers of metal for high performance IC's A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an ... | 01/04/2011 |
| 7800138 | Semiconductor device including thermally dissipating dummy pads A semiconductor device capable of improving the efficiency of dispersing heat via a dummy pad. The semiconductor device may be included in a semiconductor package, stack module, card, or system. Also disclosed is a method of manufacturing the semiconductor device. I... | 09/21/2010 |
| 7795646 | Semiconductor device A semiconductor device includes a first metal region, a plurality of vias, a plurality of second metal regions, a plurality of openings and a third metal region. The first metal region conducts source/drain current. The second metal regions are electrically connecte... | 09/14/2010 |
| 7768038 | Post vertical interconnects formed with silicide etch stop and method of making A method to form a vertical interconnect advantageous for high-density semiconductor devices. A conductive etch stop layer, preferably of cobalt silicide, is formed. The etch stop layer may be in the form of patterned lines or wires. A layer of contact material is f... | 08/03/2010 |
| 7768037 | Programmable memory cell in an integrated circuit chip A memory cell for reducing the cost and complexity of modifying a revision identifier (ID) or default register values associated with an integrated circuit (IC) chip, and a method for manufacturing the same. The cell, which may be termed a “Meta-Memory Cell” (MM... | 08/03/2010 |
| 7763911 | Peripheral circuits of three-dimensional mask-programmable memory The present invention discloses several preferred mask-programmable 3-D memory (3D-MPROM) structures, including pillar-shaped 3D-MPROM, natural-junction 3D-MPROM, interleaved 3D-MPROM, and separate 3D-MPROM. The present invention also makes further improvements to i... | 07/27/2010 |
| 7755110 | Architecture of function blocks and wirings in a structured ASIC and configurable driver cell of a logic cell zone An integrated semiconductor circuit has a regular array of logic function blocks (L) and a regular array of wiring zones (X) corresponding thereto. The wiring lines in at least one wiring layer of a wiring zone (X) are realized as line segments that are continuous w... | 07/13/2010 |
| 7755111 | Programmable power management using a nanotube structure Programmable power management using a nanotube structure is disclosed. In one embodiment, a method includes coupling a nanotube structure of an integrated circuit to a conductive surface when a command is processed, and enabling a group of transistors of the integra... | 07/13/2010 |
| 7737474 | Semiconductor device with seal ring having protruding portions A semiconductor device includes a substrate, on which an element region and a peripheral region are defined. At least one function element is to be provided in the element region, and the peripheral region surrounds the element region. The semiconductor device also ... | 06/15/2010 |
| 7723755 | Semiconductor having buried word line cell structure and method of fabricating the same Provided are a semiconductor device having a buried word line structure in which a gate electrode and a word line may be buried within a substrate to reduce the height of the semiconductor device and to reduce the degradation of the oxide layer caused by chlorine io... | 05/25/2010 |
| 7714363 | Semiconductor integrated circuit for driving the address of a display device Wiring of a PDP address driver IC is disclosed which affords an adequate permitted current capacity. In the PDP address driver IC that drives the PDP, a layer, in which a planar high voltage ground wiring layer and a planar high voltage power wiring layer are formed... | 05/11/2010 |
| 7683404 | Stacked memory and method for forming the same A stacked memory includes at least two semiconductor layers each including a memory cell array. A transistor is formed in a peripheral circuit region of an uppermost semiconductor layer of the at least two semiconductor layers. The transistor is used to operate the ... | 03/23/2010 |
| 7679109 | Semiconductor device, layout design method thereof, and layout design device using the same A semiconductor device having a multilayer structure, each layer including: a dummy pattern for ensuring a flatness thereof; a pad area in which a bonding pad is formed; an input-output circuit area in which an input-output circuit is formed, the input-output circui... | 03/16/2010 |
| 7679108 | Semiconductor memory and fabrication method for the same A semiconductor memory includes a plurality of active regions; a plurality of bit line contacts disposed on respective active regions; a plurality of first local lines formed in an island shape and in contact with upper surfaces of the plurality of bit line contacts... | 03/16/2010 |
| 7642572 | Integrated circuit having a memory cell array and method of forming an integrated circuit An integrated circuit having a memory cell array and a method of forming an integrated circuit is disclosed. One embodiment provides bitlines running along a first direction, wordlines running along a second direction substantially perpendicular to the first directi... | 01/05/2010 |
| 7642571 | Substrate core A substrate including a first patterned metallic layer, a second patterned metallic layer and an insulator is provided. One side of the first patterned metallic layer is connected to a corresponding side of the second patterned metallic layer. The first patterned me... | 01/05/2010 |
| 7622757 | Semiconductor device having multiple wiring layers A semiconductor device comprises a plurality of semiconductor elements; and a first wire and a second wire provided to connect the semiconductor elements in parallel. The first wire and the second wire include respective wires formed in multiple wiring layers. Each ... | 11/24/2009 |
| 7605409 | Semiconductor device, method of manufacturing the same, sense amplifier and method of forming the same A semiconductor device includes first and second unit circuits. Each first unit circuit has first transistors connected in series, wherein each of the first transistors includes a first gate structure having a pitch. Each second unit circuit has second transistors c... | 10/20/2009 |
| 7601994 | Display device and method for manufacturing the same According to one aspect of the present invention, at least one or more of patterns required for manufacturing a display device, such as a conductive layer which forms a wiring or an electrode and a mask, is formed by a droplet discharging method. At that time, a por... | 10/13/2009 |
| 7586132 | Power FET with low on-resistance using merged metal layers In one embodiment, relatively thin but wide metal bus strips overlying a high power FET are formed to conduct current to the source and drain narrow metal strips. A passivation layer is formed over the surface of the FET, and the passivation layer is etched to expos... | 09/08/2009 |
