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| Number | Title | Issue Date |
| 8183601 | Thin film transistor array panel for a liquid crystal display A plurality of gate lines formed on an insulating substrate, each gate line including a pad for connection to an external device; a plurality of data lines intersecting the gate lines and insulated from the gate lines, each data line including a pad for connection t... | 05/22/2012 |
| 8164119 | Semiconductor device including conductive lines with fine line width and method of fabricating the same A semiconductor device comprises a semiconductor substrate including a first core region and a second core region between which a cell array region is interposed, a first conductive line and a second conductive line extending to the first core region across the cell... | 04/24/2012 |
| 8072005 | Apparatus, method and computer program product providing radial addressing of nanowires Disclosed is a method to construct a device that includes a plurality of nanowires (NWs) each having a core and at least one shell. The method includes providing a plurality of radially encoded NWs where each shell contains one of a plurality of different shell mate... | 12/06/2011 |
| 8026537 | Semiconductor integrated circuit having an oblique global signal wiring and semiconductor integrated circuit wiring method A semiconductor integrated circuit includes a function block arranged on a substrate, a first buffering cell arranged adjacent to a first side of the function block, a second buffering cell arranged adjacent to a second side adjacent to the first side of the functio... | 09/27/2011 |
| 8024689 | Semiconductor integrated circuit apparatus with low wiring resistance It is an object to provide a semiconductor integrated circuit which can easily be designed and has a low wiring resistance, and a method and apparatus for designing the semiconductor integrated circuit. In a semiconductor integrated circuit apparatus accordin... | 09/20/2011 |
| 8004016 | Thin film transistor substrate and fabricating method thereof A thin film transistor substrate and fabricating method thereof by which the size of the thin film transistor substrate is reduced by constructing data signal supply lines, each of which supplies a pixel data voltage to a data line, with different metal lines, respe... | 08/23/2011 |
| 7982244 | Semiconductor memory device and manufacturing method thereof A semiconductor memory device includes a first block having first memory cells and first select transistors, a second block having second memory cells and second select transistors, and arranged adjacent to the first block in a first direction, the second select tra... | 07/19/2011 |
| 7960759 | Integrated circuit layout pattern for cross-coupled circuits A circuit 32 is provided comprising a first diffusion region 34 and a parallel second diffusion region 36. A sequence of N gate layers 40, 42, 46 is provided with a first and an Nth of these gate layers covering different respective ones ... | 06/14/2011 |
| 7859023 | Standard cell and semiconductor device including the same This invention prevents a break in a signal wire disposed between wire ends due to attenuation and improves production yields of devices. In a standard cell, a first signal wire extends in a first direction. Second and third signal wires extend in a second direction... | 12/28/2010 |
| 7859024 | Integrated circuit having efficiently packed decoupling capacitors An integrated circuit includes a substrate having a semiconducting surface (605) and a plurality of standard cells arranged in a plurality of rows including at least a first row (610) and a second row (615) immediately above the first row. The f... | 12/28/2010 |
| 7821040 | Thin film transistor substrate and fabricating method thereof A thin film transistor substrate and fabricating method thereof by which the size of the thin film transistor substrate is reduced by constructing data signal supply lines, each of which supplies a pixel data voltage to a data line, with different metal lines, respe... | 10/26/2010 |
| 7812375 | Non-volatile memory device and method of fabricating the same In the non-volatile memory device, a first isolation layer is formed to have a plurality of depressions each having a predetermined depth from an upper surface of the semiconductor substrate. A fin type first active region is defined by the first isolation layer and... | 10/12/2010 |
| 7800137 | Semiconductor constructions The invention includes methods of forming electrically conductive material between line constructions associated with a peripheral region or a pitch region of a semiconductor substrate. The electrically conductive material can be incorporated into an electrically-gr... | 09/21/2010 |
| 7781804 | Non-volatile memory A non-volatile memory disposed on a substrate includes active regions, a memory array, and contacts. The active regions defined by isolation structures disposed in the substrate are extended in a first direction. The memory array is disposed on the substrate and inc... | 08/24/2010 |
| 7759704 | Memory cell array comprising wiggled bit lines An integrated circuit including a memory cell array comprises transistors being arranged along parallel active area lines, bitlines, the bitlines being arranged so that an individual one intersects a plurality of the active area lines to form bitline-contacts, respe... | 07/20/2010 |
| 7692215 | Mixed-scale electronic interface Embodiments of the present invention are directed to mixed-scale electronic interfaces, included in integrated circuits and other electronic devices, that provide for dense electrical interconnection between microscale features of a predominantly microscale or submi... | 04/06/2010 |
| 7692216 | Thin film transistor array panel for a liquid crystal display A plurality of gate lines formed on an insulating substrate, each gate line including a pad for connection to an external device; a plurality of data lines intersecting the gate lines and insulated from the gate lines, each data line including a pad for connection t... | 04/06/2010 |
| 7649216 | Total ionizing dose radiation hardening using reverse body bias techniques The present invention relates to radiation hardening by design (RHBD), which employs layout and circuit techniques to mitigate the damaging effects of ionizing radiation. Reverse body biasing (RBB) of N-type metal-oxide-semiconductor (NMOS) transistors may be used t... | 01/19/2010 |
| 7635880 | Method and apparatus for proximate CMOS pixels An improved CMOS sensor integrated circuit is disclosed, along with methods of making the circuit and computer readable descriptions of the circuit. ... | 12/22/2009 |
| 7598543 | Semiconductor memory component with body region of memory cell having a depression and a graded dopant concentration A semiconductor memory component comprises at least one memory cell. The memory cell comprises a semiconductor body comprised of a body region, a drain region and a source region, a gate dielectric, and a gate electrode. The body region comprises a first conductivit... | 10/06/2009 |
| 7592649 | Memory word lines with interlaced metal layers A memory device with improved word line structure is disclosed. The memory device includes a plurality of polysilicon strips substantially parallel to each other on the substrate, the plurality of polysilicon strips arranged in two interleaved groups of a first grou... | 09/22/2009 |
| 7589362 | Configurable non-volatile logic structure for characterizing an integrated circuit device An integrated circuit (IC) device including a substrate, a plurality of device layers formed over the substrate, and a plurality of multi-level revision (MLR) structures that generate a revision code indicative of device revisions. Each MLR group structure includes ... | 09/15/2009 |
| 7544977 | Mixed-scale electronic interface Embodiments of the present invention are directed to mixed-scale electronic interfaces, included in integrated circuits and other electronic devices, that provide for dense electrical interconnection between microscale features of a predominantly microscale or submi... | 06/09/2009 |
| 7535036 | Semiconductor device and method of manufacturing the same A semiconductor device includes a semiconductor substrate divided into a memory cell region in which a memory cell is formed and a peripheral circuit region in which a peripheral circuit for driving the memory cell is formed, a plurality of conductive layers provide... | 05/19/2009 |
| 7535035 | Cross-point nonvolatile memory devices using binary metal oxide layer as data storage material layer and methods of fabricating the same A cross-point nonvolatile memory device using a binary metal oxide layer as a data storage material layer includes spaced apart doped lines disposed in a substrate. Spaced apart upper electrodes cross over the doped lines such that cross points are formed where the ... | 05/19/2009 |
| 7521736 | Electromechanical three-trace junction devices Three-trace electromechanical devices and methods of using same are described. The device of the present invention includes first and second electrically conductive elements with a nanotube ribbon (or other electromechanical elements) disposed therebetween. The nano... | 04/21/2009 |
| 7488996 | Thin film transistor array panel for a liquid crystal display A plurality of gate lines formed on an insulating substrate, each gate line including a pad for connection to an external device; a plurality of data lines intersecting the gate lines and insulated from the gate lines, each data line including a pad for connection t... | 02/10/2009 |
| 7482644 | Integrated semiconductor memory and method for electrically stressing an integrated semiconductor memory Semiconductor memories (1) have segmented word lines (5a, 5b), which in each case have a main word line (10a, 10b) made of a conductive metal and a plurality of interconnect segments (15a, ... | 01/27/2009 |
| 7436008 | Power and ground shield mesh to remove both capacitive and inductive signal coupling effects of routing in integrated circuit device A power and ground shield mesh to remove both capacitive and inductive signal coupling effects of routing in integrated circuit device. An embodiment describes the routing of a shield mesh of both power and ground lines to remove noise created by capacitive and indu... | 10/14/2008 |
| 7425735 | Multi-layer phase-changeable memory devices A phase-changeable memory device includes a phase-changeable material pattern and first and second electrodes electrically connected to the phase-changeable material pattern. The first and second electrodes are configured to provide an electrical signal to the phase... | 09/16/2008 |
| 7425739 | Nonvolatile semiconductor memory A select gate transistor has a select gate electrode composed of a first-level conductive layer and a second-level conductive layer. The first-level conductive layer has contact areas. The second-level conductive layer has its portions removed that are located above... | 09/16/2008 |
| 7425764 | Top layers of metal for high performance IC's A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an ... | 09/16/2008 |
| 7423300 | Single-mask phase change memory element A memory device. An array of memory elements is formed on a semiconductor chip. A parallel array of word lines extends in a first direction, connecting each memory element to a data source, and a parallel array of bit lines extends in a second direction, connecting ... | 09/09/2008 |
| 7420229 | Failure analysis vehicle for yield enhancement with self test at speed burnin capability for reliability testing A test vehicle for evaluating a manufacturing process for integrated circuits that uses a more space efficient layout of library driving cells arranged to produce circuits that exercise many interconnections that may be designed at the minimum design parameters of a... | 09/02/2008 |
| 7417328 | External power ring with multiple tapings to reduce IR drop in integrated circuit A power bus for use in an IC is disclosed that is configured as a grid and further formed using strips formed on I/O pads such as data I/O and multi-level voltage I/O pads. An IC is disclosed comprising a power supply I/O pad and a data I/O pad which are made of a d... | 08/26/2008 |
| 7414275 | Multi-level interconnections for an integrated circuit chip Multilevel metallization layouts for an integrated circuit chip including transistors having first, second and third elements to which metallization layouts connect. The layouts minimize current limiting mechanism including electromigration by positioning the connec... | 08/19/2008 |
| 7411295 | Circuit board, device mounting structure, device mounting method, and electronic apparatus A circuit board has a metal pattern that is formed on a surface of the circuit board to be connected with bumps in two-dimensional arrangement for mounting an electronic device that has the bumps. A plurality of the bumps which has even electrical potentials is elec... | 08/12/2008 |
| 7405450 | Semiconductor devices having high conductivity gate electrodes with conductive line patterns thereon Semiconductor devices that include a semiconductor substrate and a gate line are provided. The gate line is on the semiconductor substrate and includes a gate insulation pattern and a gate electrode which are stacked on the substrate in the order named. A spacer is ... | 07/29/2008 |
| 7402846 | Electrostatic discharge (ESD) protection structure and a circuit using the same An electrostatic discharge (ESD) protection structure is disclosed. The ESD protection structure includes an active device. The active device includes a plurality of drains. Each of the drains has a contact row and at least one body contact row. The at least one bod... | 07/22/2008 |
| 7402847 | Programmable logic circuit and method of using same A programmable logic circuit, including programmable memory element, suitable for microprocessor applications, and a method of using the circuit are disclosed. The programmable circuit includes at least one logic cell, columns and rows of wires coupled to the logic ... | 07/22/2008 |
