Quotables
"The idea that cavalry will be replaced by these iron coaches is absurd. It is little short of treasonous."
Aide-de-camp to Field Marshal Haig ; At a tank demonstration, 1916
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 8188516 | Creating integrated circuit capacitance from gate array structures Techniques for using gate arrays to create capacitive structures within an integrated circuit are disclosed. Embodiments comprise placing a gate array of P-type field effect transistors (P-fets) and N-type field effect transistors (N-fets) in an integrated circuit d... | 05/29/2012 |
| 8183600 | Semiconductor integrated circuit device with reduced cell size A technique permitting reduction in size of a standard cell is provided. In a semiconductor integrated circuit device comprising a first tap formed in a first direction to supply a power-supply potential, a second tap formed in the first direction to supply a power-... | 05/22/2012 |
| 8178905 | Layout structure of semiconductor device In a layout structure capable of independent supply of a substrate or well potential from a power supply potential, further reduction in layout area is achieved. A reinforcing power supply cell is inserted in a cell line in which a plurality of cells are arranged in... | 05/15/2012 |
| 8174052 | Standard cell libraries and integrated circuit including standard cells A standard cell library includes a first power rail, a second power rail, a third power rail, a first standard cell, and second standard cells. The first power rail extends in a first direction. The second power rail extends in the first direction, and is spaced apa... | 05/08/2012 |
| 8129759 | Semiconductor package and method using isolated Vplane to accommodate high speed circuitry ground isolation Embodiments of the invention include a semiconductor integrated circuit package that includes a substrate which can have an integrated circuit die attached thereto. The package includes a dedicated high-speed ground plane that is electrically isolated from the groun... | 03/06/2012 |
| 8120067 | Power and ground routing of integrated circuit devices with improved IR drop and chip performance An integrated circuit chip includes a semiconductor substrate having thereon a plurality of IMD layers and first conductive layers embedded in the IMD layers; a first insulating layer overlying the IMD layers and the first conductive layers; a plurality of first pow... | 02/21/2012 |
| 8110855 | Offset geometries for area reduction in memory arrays An array with cells that have adjacent similar structures that are displaced from each other across a common cell border in a direction that is not perpendicular to the cell border thus avoiding an across cell border design rule violation between the adjacent simila... | 02/07/2012 |
| 8106425 | Interconnection substrate, semiconductor chip package including the same, and display system including the same Example embodiments relate to an interconnection substrate and a semiconductor chip package and a display system including the same. The interconnection substrate may include a base film, a signal line provided on the base film, a power line provided on the base fil... | 01/31/2012 |
| 8072004 | Power and ground routing of integrated circuit devices with improved IR drop and chip performance An integrated circuit chip includes a semiconductor substrate having thereon a plurality of inter-metal dielectric (IMD) layers and a plurality of first conductive layers embedded in respective the plurality of IMD layers, wherein the first conductive layers compris... | 12/06/2011 |
| 8067790 | Semiconductor device with less power supply noise A semiconductor device includes a first power supply line; a second power supply line; a first cell arrangement area in which a first cell is arranged; and a switch area in which a switching transistor and a decoupling capacitance are arranged. The first cell is pro... | 11/29/2011 |
| 8063415 | Semiconductor device CMOS inverters are included in a standard cell. Power supply lines are electrically connected to CMOS inverters, and include lower layer interconnects and upper layer interconnect. Lower layer interconnects extend along a boundary of standard cells adjacent to each ... | 11/22/2011 |
| 8063416 | Semiconductor device In a substrate power supply cell, a portion of a substrate power supply wiring is exposed by forming a power supply wiring in a U-shape, and a connection portion to an upper-layer wiring is provided at a boundary portion of the substrate power supply cell. Thereby, ... | 11/22/2011 |
| 8063417 | Integrated circuit device and method for forming the same In an integrated circuit device, element power supply lines connected to a circuit containing a plurality of cells, element ground lines connected thereto, a trunk power supply line connected to each of the element power supply lines, and a trunk ground line connect... | 11/22/2011 |
| 8058672 | Semiconductor device and display device It is an object of the invention to provide a thin, lightweight, high performance, and low in cost semiconductor device and a display device by reducing an arrangement area required for a power supply wiring and a ground wiring of a functional circuit and decreasing... | 11/15/2011 |
| 8044438 | Liquid crystal display and substrate thereof Disclosed are a liquid crystal display and a substrate for the same. The substrate comprises first wires formed in one direction on the substrate; second wires intersecting and insulated from the first wires; pixel electrodes formed in pixel regions defined by the f... | 10/25/2011 |
| 8035134 | Forward body bias-controlled semiconductor integrated circuit In a first functional block, a source voltage input terminal of a PMOS transistor and a substrate voltage input terminal of an NMOS transistor are connected to their voltage supply terminals, respectively. The substrate voltage input terminal of the PMOS transistor ... | 10/11/2011 |
| 8035135 | Semiconductor memory device To facilitate counting of memory cells in failure analysis, without limiting the arrangement of memory cells or increasing the number of processes. A memory cell array region 3 in which memory cells 3a are formed in a repetitive pattern is forme... | 10/11/2011 |
| 7994543 | Via antenna fix in deep sub-micron circuit designs A filler cell for use in fabricating an integrated circuit. The filler cell couples a power supply rail of an adjacent logic cell to a power supply rail of another adjacent logic cell. The filler cell also has a diode to bleed charge accumulated on the power rails o... | 08/09/2011 |
| 7994542 | Semiconductor device A semiconductor device of the present invention comprises a logic circuit to which a power supply voltage, a sub-power supply voltage, a ground voltage and a sub-ground voltage are supplied; a driver for generating the sub-power supply voltage and the sub-ground vol... | 08/09/2011 |
| 7989849 | Apparatuses and methods for efficient power rail structures for cell libraries An integrated circuit has a power rail formed of a first wire in a lower metal layer and a second wire in an upper metal layer and that run in the same direction in their respective layers. A number of vias connect the first and second wires, to form a sandwich powe... | 08/02/2011 |
| 7973340 | Semiconductor integrated circuit with improved power supply system Cells are formed on a substrate. First and second cell power wiring lines extend in a first direction on the substrate. First and second intermediate layer power wiring lines are formed on the first and second cell power lines. First upper layer power wiring lines a... | 07/05/2011 |
| 7968917 | Semiconductor memory device There is provided a semiconductor memory device including: a first wiring layer; a second wiring layer; a third wiring layer; a memory array region; a first gate array region being formed at a region at which the first wiring layer, the second wiring layer and the t... | 06/28/2011 |
| 7902573 | Semiconductor device including vertical MOS transistors A semiconductor device includes: a plurality of vertical MOS transistors sharing a gate electrode (2) of a first conductivity type; first semiconductor pillars (3, 4 and 5) with a gate insulating film (18) formed therearound, across the g... | 03/08/2011 |
| RE41963 | Semiconductor memory device A semiconductor memory device is constructed to include a memory cell formed by a plurality of transistors, wherein each of gate wiring layers of all of the transistors forming the memory cell is arranged to extend in one direction. ... | 11/30/2010 |
| 7834381 | Layout of power source regions and power switch regions in a semiconductor integrated circuit device Repeaters are arranged at arbitrary positions to substantially improve transmission speed of a signal. In the semiconductor integrated circuit device 1, repeater regions 10 where repeaters are provided as relay points for wiring are provided in the cen... | 11/16/2010 |
| 7821038 | Power and ground routing of integrated circuit devices with improved IR drop and chip performance An integrated circuit chip with reduced IR drop and improved chip performance is disclosed. The integrated circuit chip includes a semiconductor substrate having thereon a plurality of inter-metal dielectric (IMD) layers and a plurality of copper metal layers embedd... | 10/26/2010 |
| 7821039 | Layout architecture for improving circuit performance An integrated circuit structure includes an integrated circuit structure including a PMOS transistor including a first gate electrode; a first source region; and a first drain region; an NMOS transistor including a second gate electrode, wherein the first gate elect... | 10/26/2010 |
| 7800136 | Semiconductor integrated circuit and semiconductor integrated circuit design method The height H of several kinds of basic cell are made the same and several kinds of macro cell which have a length which is an integral multiplication of the height H of this basic cell, are prepared, the basic cell and macro cell are mixed and the circuit of a perip... | 09/21/2010 |
| 7795645 | Semiconductor integrated circuit It is an object of the present invention to provide a semiconductor integrated circuit having a chip layout that reduces line length to achieve faster processing. A cache comprises a TAG memory module and a cache data memory module. The cache data memory module is d... | 09/14/2010 |
| 7750375 | Power line layout techniques for integrated circuits having modular cells This invention discloses a integrated circuit (IC) chip having a plurality of modular cells, the chip comprises a first modular cell having a first metal layer, which contains at least two power lines independent of each other; and a second modular cell, juxtaposed ... | 07/06/2010 |
| 7737473 | Integrated circuit device and method for forming the same In an integrated circuit device, element power supply lines connected to a circuit containing a plurality of cells, element ground lines connected thereto, a trunk power supply line connected to each of the element power supply lines, and a trunk ground line connect... | 06/15/2010 |
| 7667245 | Driving circuit of a liquid crystal display panel A driving circuit of a liquid crystal display panel includes a substrate, a plurality of driver IC chips located on the substrate, a current supplier, and a first conductive wire set. The first conductive wire set has a plurality of conductive wire segments for conn... | 02/23/2010 |
| 7612391 | Semiconductor integrated circuit device In a low power consumption mode in which prior data is retained upon power shutdown, the return speed thereof is increased. While use of an existent data retaining flip-flop may be considered, this is not preferred since it increases area overhead such as enlargemen... | 11/03/2009 |
| 7479666 | Driving circuit of a liquid crystal display panel A driving circuit of a liquid crystal display panel includes a substrate, a plurality of driver IC chips located on the substrate, a current supplier, and a first conductive wire set. The first conductive wire set has a plurality of conductive wire segments for conn... | 01/20/2009 |
| 7476915 | Semiconductor integrated circuit including a first region and a second region A semiconductor integrated circuit effectively makes use of wiring channels of wiring formed by a damascene method. When first cells are used, since the M1 power source lines are laid out at positions spaced away from a boundary between the cells, the power s... | 01/13/2009 |
| 7468530 | Structure and method for failure analysis in a semiconductor device In a method and structure for semiconductor failure analysis, the structure comprises: a plurality of analytic fields disposed on a predetermined area of a semiconductor device; semiconductor transistors arranged in each of the analytic fields, the semiconductor tra... | 12/23/2008 |
| 7465974 | Integrated circuit device and method for forming the same In an integrated circuit device, element power supply lines connected to a circuit containing a plurality of cells, element ground lines connected thereto, a trunk power supply line connected to each of the element power supply lines, and a trunk ground line connect... | 12/16/2008 |
| 7456447 | Semiconductor integrated circuit device In a semiconductor integrated circuit device, a VDD wiring trace and a GND wiring trace are routed along an N-well and a P-well, respectively, within a substrate. A substrate-bias VDD2 wiring trace is routed in a direction that intersects the VDD wiring trace and GN... | 11/25/2008 |
| 7439943 | Electro-optical device, wiring substrate, and electronic apparatus The invention provides an electro-optical device in which a voltage drop due to the wiring resistance of a cathode is reduced and therefore steady image signals are transmitted such that erroneous image display, such as low contrast, is reduced or prevented. The inv... | 10/21/2008 |
| 7436008 | Power and ground shield mesh to remove both capacitive and inductive signal coupling effects of routing in integrated circuit device A power and ground shield mesh to remove both capacitive and inductive signal coupling effects of routing in integrated circuit device. An embodiment describes the routing of a shield mesh of both power and ground lines to remove noise created by capacitive and indu... | 10/14/2008 |
