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| Number | Title | Issue Date |
| 8178904 | Gate array A gate array of a semiconductor substrate on which plural unit cells are arranged in parallel, the unit cells having the same pattern that includes a source potential region VDD, a PMOS, an NMOS and a ground potential region GND. Metal wiring lines being formed, wit... | 05/15/2012 |
| 8178903 | Semiconductor device A semiconductor device in accordance with an exemplary aspect of the present invention includes: an even number of transistor pairs; connection nodes connecting the n-type transistors and the p-type transistors of the transistor pairs; and inter-gate wiring lines co... | 05/15/2012 |
| 8138525 | Integrated circuit including at least three linear-shaped conductive structures of different length each forming gate of different transistor A cell of a semiconductor device includes a substrate portion formed to include at least one p-type diffusion region and at least one n-type diffusion region separated by non-active regions. The cell includes a gate electrode level including a number of conductive f... | 03/20/2012 |
| 8134186 | Integrated circuit including at least three linear-shaped conductive structures at equal pitch including linear-shaped conductive structure having non-gate portion length greater than gate portion length A cell of a semiconductor device includes a diffusion level including a plurality of diffusion regions separated by inactive regions. The cell also includes a gate electrode level including conductive features defined to extend in only a first parallel direction. Ad... | 03/13/2012 |
| 8134185 | Integrated circuit having gate electrode level region including at least seven linear-shaped conductive structures at equal pitch including linear-shaped conductive structure forming transistors of two different types and at least three linear-shaped conductive structures having aligned ends A layout of a cell of a semiconductor device is disclosed to include a diffusion level layout including a plurality of diffusion region layout shapes, including a p-type and an n-type diffusion region separated by a central inactive region. The layout of the cell in... | 03/13/2012 |
| 8134183 | Integrated circuit including linear-shaped conductive structures that have gate portions and extending portions of different size A semiconductor device includes a substrate portion having a plurality of diffusion regions defined therein. A gate electrode level region is formed above the substrate portion to include conductive features defined to extend in only a first parallel direction. Adja... | 03/13/2012 |
| 8134184 | Integrated circuit having gate electrode level region including at least four linear-shaped conductive structures with some outer-contacted linear-shaped conductive structures having larger outer extending portion than inner extending portion A layout of a cell of a semiconductor device is disclosed to include a diffusion level layout including a plurality of diffusion region layout shapes, including a p-type and an n-type diffusion region separated by a central inactive region. The layout of the cell in... | 03/13/2012 |
| 8129752 | Integrated circuit including a linear-shaped conductive structure forming one gate electrode and having length greater than or equal to one-half the length of linear-shaped conductive structure forming two gate electrodes A semiconductor device includes a substrate portion including a plurality of diffusion regions defined in a non-symmetrical manner relative to a virtual bisecting line. A gate electrode level region above the substrate portion includes a number of conductive feature... | 03/06/2012 |
| 8129756 | Integrated circuit including at least six linear-shaped conductive structures forming gate electrodes of transistors with at least two different extension distances beyond conductive contacting structures A cell of a semiconductor device is disclosed to include a diffusion level including a plurality of diffusion regions separated by inactive regions. The cell also includes a gate electrode level including conductive features defined to extend in only a first paralle... | 03/06/2012 |
| 8129755 | Integrated circuit with gate electrode level including at least four linear-shaped conductive structures of equal length and equal pitch with linear-shaped conductive structure forming one transistor A cell of a semiconductor device is disclosed to include a diffusion level including a plurality of diffusion regions separated by inactive regions. The cell also includes a gate electrode level including a number of conductive features defined to extend in only a f... | 03/06/2012 |
| 8129751 | Integrated circuit including at least six linear-shaped conductive structures forming gate electrodes and including four conductive contacting structures having at least two different connection distances A semiconductor device includes a substrate portion having a plurality of diffusion regions defined therein in a non-symmetrical manner relative to a virtual line defined to bisect the substrate portion. The semiconductor device includes a gate electrode level regio... | 03/06/2012 |
| 8129753 | Integrated circuit including gate electrode level region including at least seven linear-shaped conductive structures of equal length positioned at equal pitch with at least two linear-shaped conductive structures each forming one transistor and having extending portion sized greater than gate portion A layout of a cell of a semiconductor device is disclosed to include a diffusion level layout including a plurality of diffusion region layout shapes, including p-type and n-type diffusion regions. The layout of the cell also includes a gate electrode level layout d... | 03/06/2012 |
| 8129750 | Integrated circuit including at least six linear-shaped conductive structures forming gate electrodes of transistors with at least two linear-shaped conductive structures of different length A semiconductor device includes a substrate portion having a plurality of diffusion regions defined therein in a non-symmetrical manner relative to a virtual line defined to bisect the substrate portion. The semiconductor device includes a gate electrode level regio... | 03/06/2012 |
| 8129758 | Semiconductor element and manufacturing method therefor A semiconductor device includes: a semiconductor layer including silicon carbide, which has been formed on a substrate; a semiconductor region 15 of a first conductivity type defined on the surface of the semiconductor layer 10; a semiconductor region ... | 03/06/2012 |
| 8129754 | Integrated circuit with gate electrode level including at least six linear-shaped conductive structures forming gate electrodes of transisters with at least one pair of linear-shaped conductive structures having offset ends A cell of a semiconductor device is disclosed to include a diffusion level including a plurality of diffusion regions separated by inactive regions. The cell also includes a gate electrode level including a number of conductive features defined to extend in only a f... | 03/06/2012 |
| 8129757 | Integrated circuit including at least six linear-shaped conductive structive structures at equal pitch including at least two linear-shaped conductive structures having non-gate portions of different length A cell of a semiconductor device includes a diffusion level including a plurality of diffusion regions separated by inactive regions. The cell also includes a gate electrode level including conductive features defined to extend in only a first parallel direction. Ad... | 03/06/2012 |
| 8125005 | Semiconductor element and method for manufacturing same A semiconductor device includes: a semiconductor layer 10; a semiconductor region 15s of a first conductivity type defined on the surface 10s of the semiconductor layer; a semiconductor region 14s of a second conducti... | 02/28/2012 |
| 8110854 | Integrated circuit device with linearly defined gate electrode level region and shared diffusion region of first type connected to shared diffusion region of second type through at least two interconnect levels A semiconductor device includes a substrate portion having a plurality of diffusion regions defined therein. The semiconductor device includes a gate electrode level region including a number of conductive features defined to extend in only a first parallel directio... | 02/07/2012 |
| 8101975 | Integrated circuit device with gate level region including non-gate linear conductive segment positioned within 965 nanometers of four transistors of first type and four transistors of second type A semiconductor device includes a substrate portion having a plurality of diffusion regions defined therein. The semiconductor device includes a gate electrode level region including a number of conductive features defined to extend in only a first parallel directio... | 01/24/2012 |
| 8089102 | Method for fabricating integrated circuit having three or more linear-shaped gate electrode level conductive segments of both equal length and equal pitch A semiconductor device includes a substrate portion having a plurality of diffusion regions defined therein. A gate electrode level region is formed above the substrate portion to include conductive features defined to extend in only a first parallel direction. Adja... | 01/03/2012 |
| 8089098 | Integrated circuit device and associated layout including linear gate electrodes of different transistor types next to linear-shaped non-gate conductive segment A restricted layout region in a layout of a semiconductor device is disclosed to include a diffusion level layout including a plurality of diffusion region layout shapes. The plurality of diffusion region layout shapes are defined in a non-symmetrical manner relativ... | 01/03/2012 |
| 8089101 | Integrated circuit device with gate electrode level region including two side-by-side ones of at least three linear-shaped conductive structures electrically connected to each other through non-gate level A semiconductor device includes a substrate portion having a plurality of diffusion regions defined therein. A gate electrode level region is formed above the substrate portion to include conductive features defined to extend in only a first parallel direction. Adja... | 01/03/2012 |
| 8089103 | Integrated circuit device with gate level region including at least three linear-shaped conductive segments having offset line ends and forming three transistors of first type and one transistor of second type A semiconductor device includes a substrate portion having a plurality of diffusion regions defined therein. A gate electrode level region is formed above the substrate portion to include conductive features defined to extend in only a first parallel direction. Adja... | 01/03/2012 |
| 8089104 | Integrated circuit with gate electrode level region including multiple linear-shaped conductive structures forming gate electrodes of transistors and including uniformity extending portions of different size A cell layout of a semiconductor device includes a diffusion level layout including a plurality of diffusion region layout shapes, including p-type and n-type diffusion regions. The cell layout also includes a gate electrode level layout defined to include linear-sh... | 01/03/2012 |
| 8089099 | Integrated circuit device and associated layout including gate electrode level region of 965 NM radius with linear-shaped conductive segments on fixed pitch A restricted layout region includes a diffusion level layout including a number of diffusion region layout shapes to be formed within a substrate portion of a semiconductor device. The diffusion region layout shapes define at least one p-type diffusion region and at... | 01/03/2012 |
| 8089100 | Integrated circuit with gate electrode level region including at least four linear-shaped conductive structures forming gate electrodes of transistors and including extending portions of at least two different sizes A restricted layout region includes a diffusion level layout including diffusion region layout shapes that define at least one p-type diffusion region and at least one n-type diffusion region separated by a central inactive region. A gate electrode level layout is d... | 01/03/2012 |
| 8072003 | Integrated circuit device and associated layout including two pairs of co-aligned complementary gate electrodes with offset gate contact structures A semiconductor device includes a substrate portion that includes a plurality of diffusion regions that include at least one p-type diffusion region and at least one n-type diffusion region. A gate electrode level region is formed above the substrate portion to incl... | 12/06/2011 |
| 8063414 | Compact standard cell A standard cell, placed between a power rail and a ground rail in an integrated circuit, has active areas with connecting arms that extend beneath the power rail and ground rail. The connecting arms conduct current between the power and ground rails and the source r... | 11/22/2011 |
| 8058671 | Semiconductor device having at least three linear-shaped electrode level conductive features of equal length positioned side-by-side at equal pitch A semiconductor device includes a substrate portion that includes a plurality of diffusion regions that include at least one p-type diffusion region and at least one n-type diffusion region. A gate electrode level region is formed above the substrate portion to incl... | 11/15/2011 |
| 8044437 | Integrated circuit cell architecture configurable for memory or logic elements An improved integrated circuit cell architecture is provided for configurability between a memory cell or logic elements. The cell architecture is configured on variable layers above a first layer of metal, with the first layer of metal and layers therebelow reserve... | 10/25/2011 |
| 8039874 | Semiconductor integrated circuit According to an aspect of the present invention, there is provided a semiconductor IC that includes a plurality of standard cells arranged in a first direction on a semiconductor substrate, and a first diffusion layer connected to a first power source and a second d... | 10/18/2011 |
| 8035133 | Semiconductor device having two pairs of transistors of different types formed from shared linear-shaped conductive features with intervening transistors of common type on equal pitch A semiconductor device includes a substrate portion having a plurality of diffusion regions defined in a non-symmetrical manner relative to a virtual line defined to bisect the substrate portion. A gate electrode level region is formed above the substrate portion to... | 10/11/2011 |
| 8030689 | Integrated circuit device and associated layout including separated diffusion regions of different type each having four gate electrodes with each of two complementary gate electrode pairs formed from respective linear conductive segment A semiconductor device includes a substrate portion that includes a plurality of diffusion regions that include at least one p-type diffusion region and at least one n-type diffusion region. A gate electrode level region is formed above the substrate portion to incl... | 10/04/2011 |
| 8022441 | Semiconductor device and associated layouts having transistors formed from six linear conductive segments with gate electrode-to-gate electrode connection through single interconnect level and common node connection through different interconnect level A semiconductor device is disclosed as having a substrate portion that includes a plurality of diffusion regions that include at least one p-type diffusion region and at least one n-type diffusion region. A gate electrode level region is formed above the substrate p... | 09/20/2011 |
| 8013363 | Nonvolatile nanotube diodes and nonvolatile nanotube blocks and systems using same and methods of making same Under one aspect, a nonvolatile nanotube diode includes: a substrate; a semiconductor element disposed over the substrate, the semiconductor element having an anode and a cathode and capable of forming an electrically conductive pathway between the anode and the cat... | 09/06/2011 |
| 7989848 | Semiconductor device having at least four side-by-side electrodes of equal length and equal pitch with at least two transistor connections to power or ground A substrate portion of a semiconductor device is formed to include a plurality of diffusion regions that are defined in a non-symmetrical manner relative to a virtual line defined to bisect the substrate portion. A gate electrode level region is formed above the sub... | 08/02/2011 |
| 7989847 | Semiconductor device having linear-shaped gate electrodes of different transistor types with uniformity extending portions of different lengths A restricted layout region includes a diffusion level layout that includes a number of diffusion region layout shapes to be formed within a portion of a substrate of a semiconductor device. The diffusion region layout shapes define at least one p-type diffusion regi... | 08/02/2011 |
| 7989846 | Semiconductor device with three-dimensional field effect transistor structure The semiconductor device includes first and second common source semiconductor layers respectively extending in a first direction, first and second logic gate circuits respectively composed of at least one three-dimensional P-type FET and a three-dimensional N-type ... | 08/02/2011 |
| 7977709 | MOS transistor and semiconductor device According to one embodiment of the present invention, a MOS transistor includes a semiconductor layer including a source region, a drain region, and a channel region disposed between the source region and the drain region. A gate structure is arranged above the chan... | 07/12/2011 |
| 7952118 | Semiconductor device having different metal gate structures A semiconductor includes a channel region in a semiconductor substrate, a gate dielectric film on the channel region, and a gate on the gate dielectric film. The gate includes a doped metal nitride film, formed from a nitride of a first metal and doped with a second... | 05/31/2011 |
