Famous Patents
3M employee and church chorister Art Fry needed something to temporarily mark pages in his hymnal. He was in luck because his colleague, Spencer Silver, accidentally developed a glue that was too weak for other purposes. After initially discouraging consumer response, Post-it Notes became a hit in 1979.
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| Number | Title | Issue Date |
| 7939857 | Composite device having three output terminals A composite device includes a depletion mode FET coupled to a bipolar transistor. The FET includes gate, drain and source terminals, and the bipolar transistor includes base, collector and emitter terminals. The collector terminal of the bipolar transistor and the s... | 05/10/2011 |
| 7898006 | Integrated circuit having memory cells and method of manufacture An integrated circuit having memory cells and a method of manufacture is disclosed. One embodiment provides a switching active volume and a selection transistor coupled in series between a first electrode and a second electrode. The selection transistor is a vertica... | 03/01/2011 |
| 7838909 | Semiconductor device with trench structure A semiconductor device includes a common diffusion structure formed in each region of a substrate in which semiconductor components are formed. The diffusion structures are separated into sections by trenches to form semiconductor components. The trenches define siz... | 11/23/2010 |
| 7622756 | Semiconductor device and radio communication device A technology which allows a reduction in the thermal resistance of a semiconductor device and the miniaturization thereof is provided. The semiconductor device has a plurality of unit transistors Q, transistor formation regions 3a, 3b, an... | 11/24/2009 |
| 7598541 | Semiconductor device comprising transistor pair isolated by trench isolation A semiconductor device has transistors (P1,P10,P11) formed in an active region (22) isolated by a trench isolation region, and a predetermined circuit including a first and second transistors (P10,P11) that require symmetry ... | 10/06/2009 |
| 7405434 | Quantum dot conjugates in a sub-micrometer fluidic channel A nanofluidic channel fabricated in fused silica with an approximately 500 nm square cross section was used to isolate, detect and identify individual quantum dot conjugates. The channel enables the rapid detection of every fluorescent entity in solution. A laser of... | 07/29/2008 |
| 7402846 | Electrostatic discharge (ESD) protection structure and a circuit using the same An electrostatic discharge (ESD) protection structure is disclosed. The ESD protection structure includes an active device. The active device includes a plurality of drains. Each of the drains has a contact row and at least one body contact row. The at least one bod... | 07/22/2008 |
| 7394156 | Semiconductor integrated circuit device and method of producing the same A semiconductor integrated circuit device has a plurality of CMOS-type base cells arranged on a semiconductor substrate and m wiring layers, and gate array type logic cells are composed of the base cells and the wiring layers. Wiring within and between the logic cel... | 07/01/2008 |
| 7372155 | Top layers of metal for high performance IC's A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length-by making efficient use of polyimide or polymer as an ... | 05/13/2008 |
| 7348610 | Multiple layer and crystal plane orientation semiconductor substrate A semiconductor on insulator substrate and a method of fabricating the substrate. The substrate including: a first crystalline semiconductor layer and a second crystalline semiconductor layer; and an insulating layer bonding a bottom surface of the first crystalline... | 03/25/2008 |
| 7321139 | Transistor layout for standard cell with optimized mechanical stress effect A layout for a transistor in a standard cell is disclosed. The layout for a transistor includes an active region with at least one portion having a first edge and at least one portion having a second edge all perpendicular to a channel of the transistor; and a gate ... | 01/22/2008 |
| 7271472 | Circuit board and method for producing a circuit board A circuit board comprises a dielectric layer, a net of first power supply lines for providing a first reference voltage plane and a net of second power supply lines for providing a second reference voltage plane. The nets of first and second power supply lines are a... | 09/18/2007 |
| 7265006 | Method of fabricating heterojunction devices integrated with CMOS A method of fabricating heterojunction devices, in which heterojunction devices are epitaxially formed on active area regions surrounded by field oxide regions and containing embedded semiconductor wells. The epitaxial growth of the heterojunction device layers may ... | 09/04/2007 |
| 7217966 | Self-protecting transistor array A transistor array is self-protected from an electrostatic discharge (ESD) event which can cause localized ESD damage by integrating an ESD protection device into the transistor array. The ESD protection device operates as a transistor during normal operating condit... | 05/15/2007 |
| 7215562 | Semiconductor storage device A semiconductor storage device in which a pair of wiring lines extending in a first direction are arranged repeatedly with a predetermined pitch, comprising: a group of pair transistors in which a plurality of pair transistors is arranged according to a repetition u... | 05/08/2007 |
| 7161216 | Depletion-mode transistor that eliminates the need to separately set the threshold voltage of the depletion-mode transistor A semiconductor circuit with a depletion-mode transistor is formed with a method that eliminates the need for a separate mask and implant step to set the threshold voltage of the depletion-mode transistor. As a result, the method of the present invention reduces the... | 01/09/2007 |
| 7135722 | Wiring layout of semiconductor device and design method of the same A semiconductor device is the semiconductor device which includes more than one field effect transistor having a gate electrode to which an electrical interconnect wire is connected and a gate insulation film with a thickness of 6.0 nm or less and which comprises a ... | 11/14/2006 |
| 7119383 | Arrangement of wiring lines including power source lines and channel wirings of a semiconductor integrated circuit having plural cells A semiconductor integrated circuit effectively makes use of wiring channels of wiring formed by a damascene method. When first cells are used, since the M1 power source lines are laid out at positions spaced away from a boundary between the cells, the power source l... | 10/10/2006 |
| 7115920 | FinFET transistor and circuit A drive strength tunable FinFET, a method of drive strength tuning a FinFET, a drive strength ratio tuned FinFET circuit and a method of drive strength tuning a FinFET, wherein the FinFET has either at least one perpendicular and at least one angled fin or has at le... | 10/03/2006 |
| 7053424 | Semiconductor integrated circuit device and its manufacture using automatic layout A semiconductor integrated circuit device has: a semiconductor substrate defining a plurality of rows, each row including areas for a sequence of cells; a plurality of active regions disposed in each of the rows constituting semiconductor elements of associated cell... | 05/30/2006 |
| 7026690 | Memory devices and electronic systems comprising integrated bipolar and FET devices The invention includes BIFETRAM devices. Such devices comprise a bipolar transistor in combination with a field effect transistor (FET) in a three-dimensional stacked configuration. The memory devices can be incorporated within semiconductor-on-insulator (SOI) const... | 04/11/2006 |
| 6998698 | Memory cell with a perovskite structure varistor The present invention provides a memory cell having a variable resistor as a memory element, and also provides a memory device comprising the memory cells. The variable resistor is made of a thin-film material (for example, PCMO) or the like having a perovskite stru... | 02/14/2006 |
| 6995432 | Semiconductor device having a gate oxide film with some NTFTS with LDD regions and no PTFTS with LDD regions A MIS type semiconductor device and a method for fabricating the same characterized in that impurity regions are selectively formed on a semiconductor substrate or semiconductor thin film and are activated by radiating laser beams or a strong light equivalent theret... | 02/07/2006 |
| 6979908 | Input/output architecture for integrated circuits with efficient positioning of integrated circuit elements A described embodiment of the present invention includes an integrated circuit having a plurality of I/O modules. The I/O modules include a bond pad formed on a substrate. The I/O modules also include an electrostatic discharge device formed in the substrate. The el... | 12/27/2005 |
| 6972442 | Efficiently fabricated bipolar transistor One embodiment is a method for fabricating the base of a bipolar transistor where the method comprises placing a first wafer in an undoped epi chamber. Next a first undoped base layer is grown over the first wafer. After growing the first undoped base layer, the fir... | 12/06/2005 |
| 6961111 | Display device and method of producing same A driver circuit-integrated type active matrix substrate 212 has, on a glass substrate 210, a liquid crystal display unit 221 including a matrix array composed of thin film transistors, and driver circuits 224–226 for driving the liquid... | 11/01/2005 |
| 6949764 | Fully-depleted-collector silicon-on-insulator (SOI) bipolar transistor useful alone or in SOI BiCMOS A bipolar transistor structure is described incorporating an emitter, base, and collector having a fully depleted region on an insulator of a Silicon-On-Insulator (SOI) substrate without the need for a highly doped subcollector to permit the fabrication of vertical ... | 09/27/2005 |
| 6903386 | Transistor with means for providing a non-silicon-based emitter A transistor includes a means for providing a non-silicon-based emitter with a flexible structure to relieve lattice mis-match between the emitter and the base. ... | 06/07/2005 |
| 6881989 | Semiconductor integrated circuit having high-density base cell array A base cell is configured such that P-type regions 11 to 13 are arrayed in a column direction in an N-type well 10, N-type regions 21 to 23 are arrayed in a column direction in a P-type well 20 next to the N-type well, gate ... | 04/19/2005 |
| 6870184 | Mechanically-stable BJT with reduced base-collector capacitance A bipolar junction transistor (BJT) requires the fabrication of a BJT structure and of a support post which is adjacent to, but physically and electrically isolated from, the BJT structure. The BJT structure includes a semi-insulating substrate, a subcollector, a co... | 03/22/2005 |
| 6849871 | Fully-depleted-collector silicon-on-insulator (SOI) bipolar transistor useful alone or in SOI BiCMOS A bipolar transistor structure is described incorporating an emitter, base, and collector having a fully depleted region on an insulator of a Silicon-On-Insulator (SOI) substrate without the need for a highly doped subcollector to permit the fabrication of vertical ... | 02/01/2005 |
| 6841810 | Cell structure for bipolar integrated circuits and method In one embodiment, a bipolar cell (31) includes a cell boundary (32) that defines a cell active area (33), a first array of bipolar transistors (41) is formed within the cell active area (33) and configured for a first function. Th... | 01/11/2005 |
| 6838709 | Bipolar transistor A bipolar transistor includes the first group of transistors 610a, the second group of transistors 610b, the third group of transistors 610c and the fourth group of transistors 610d. The groups of transistors h... | 01/04/2005 |
| 6835969 | Split-channel high electron mobility transistor (HEMT) device A transistor structure having an gallium arsenide (GaAs) semiconductor substrate; a lattice match layer; an indium aluminum arsenide (InAlAs) barrier layer disposed over the lattice match layer; an InyGa1-yAs lower channel layer disposed on the... | 12/28/2004 |
| 6803634 | Stabilization in device characteristics of a bipolar transistor that is included in a semiconductor device with a CMOSFET In the manufacturing process of a Bi-CMOS semiconductor device, which includes a CMOSFET and a bipolar transistor, the steps for forming a well region, source regions, and drain regions of the CMOSFET are also used for forming the bipolar transistor. One of the step... | 10/12/2004 |
| 6784063 | Method for fabricating BiCMOS transistor The present invention discloses a method for fabricating a BiCMOS transistor, which improves the high frequency characteristics of a bipolar transistor by reducing base resistance and a parasitic capacitance between the base and collector. The method comprises the s... | 08/31/2004 |
| 6774411 | Bipolar transistor with reduced emitter to base capacitance According to a disclosed embodiment, a base region is grown on a transistor region. A dielectric layer is next deposited over the base region. The dielectric layer can comprise, for example, silicon dioxide, silicon nitride, or a suitable low-k dielectric. Subsequen... | 08/10/2004 |
| 6768143 | Structure and method of making three finger folded field effect transistors having shared junctions An integrated circuit including a field effect transistor (FET) is provided in which the gate conducter has an even number of fingers disposed between alternating source and drain regions of a substrate. The fingers are disposed in a pattern over an area of the subs... | 07/27/2004 |
| RE38545 | Semiconductor memory device A semiconductor memory device having a plurality of memory cells each comprising two CMOS inverters cross-coupled to each other and arranged at intersections between a plurality of word lines extending in a column direction and a plurality of complementary data line... | 07/06/2004 |
| 6747322 | Semiconductor device, memory system and electronic apparatus A semiconductor device having a memory cell including first and second load transistors, first and second driver transistors, and first and second transfer transistors. The semiconductor device includes first and second gate—gate electrode layers, first and second... | 06/08/2004 |
