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| Number | Title | Issue Date |
| 8178902 | CMOS transistor with dual high-k gate dielectric and method of manufacture thereof A CMOS device with transistors having different gate dielectric materials and a method of manufacture thereof. A CMOS device is formed on a workpiece having a first region and a second region. A first gate dielectric material is deposited over the second region. A f... | 05/15/2012 |
| 8154055 | CMOS image sensor and method for fabricating the same A complementary metal-oxide semiconductor (CMOS) image sensor includes a photodiode formed in a substrate structure, first to fourth gate electrodes formed over the substrate structure, spacers formed on both sidewalls of the first to fourth gate electrodes and fill... | 04/10/2012 |
| 8143651 | Nested and isolated transistors with reduced impedance difference A processing layer, such as silicon, is formed on a metal silicide contact followed by a metal layer. The silicon and metal layers are annealed to increase the thickness of the metal silicide contact. By selectively increasing the thickness of silicide contacts, R | 03/27/2012 |
| 8084787 | PMD liner nitride films and fabrication methods for improved NMOS performance Semiconductor devices (102) and fabrication methods (10) are provided, in which a nitride film (130) is formed over NMOS transistors to impart a tensile stress in ail or a portion of the NMOS transistor to improve carrier mobility. The nitride l... | 12/27/2011 |
| 8035132 | Display device and semiconductor device A display device of high definition, multiple colors and low power consumption includes a display panel having a pixel section in which pixels are arrayed in the form of a matrix at the cross points of a plurality of data lines and a plurality of scanning lines, a s... | 10/11/2011 |
| 8026536 | Semiconductor device having a dummy gate A semiconductor device includes a plurality of MOS transistors, wherein each of the MOS transistors has a drain region, a pair of source regions sandwiching therebetween the drain region, and a pair of normal gates each overlying a space between the drain region and... | 09/27/2011 |
| 7868359 | Semiconductor device In a semiconductor device including multiple unit cells arranged in an array, transistors are affected by a stress from an STI at different degrees depending on the position in the array. As a result, a variation occurs in transistor characteristic. In a semiconduct... | 01/11/2011 |
| 7863653 | Method of enhancing hole mobility A semiconductor device is provided comprising an oxide layer over a first silicon layer and a second silicon layer over the oxide layer, wherein the oxide layer is between the first silicon layer and the second silicon layer. The first silicon layer and the second s... | 01/04/2011 |
| 7842975 | Dynamic array architecture A semiconductor device includes a substrate portion and a number of diffusion regions defined within the substrate portion. The diffusion regions are separated from each other by a non-active region of the substrate portion. The semiconductor device includes a numbe... | 11/30/2010 |
| 7838908 | Semiconductor device having dual metal gates and method of manufacture A semiconductor device includes: a semiconductor substrate; a PFET formed on the substrate, the PFET includes a SiGe layer disposed on the substrate, a high-K dielectric layer disposed on the SiGe layer, a first metallic layer disposed on the high-k dielectric layer... | 11/23/2010 |
| 7825437 | Unity beta ratio tri-gate transistor static random access memory (SRAM) In general, in one aspect, a method includes forming N-diffusion and P-diffusion fins in a semiconductor substrate. A P-diffusion gate layer is formed over the semiconductor substrate and removed from the N-diffusion fins. A pass-gate N-diffusion gate layer is forme... | 11/02/2010 |
| 7808017 | Semiconductor integrated circuit A semiconductor integrated circuit having a first p-type MOS transistor; a first n-type MOS transistor; a second p-type MOS transistors; a and second n-type MOS transistors having fourth gate electrodes disposed so as to be adjacent to the second diffused regions of... | 10/05/2010 |
| 7800135 | Power semiconductor device and method of manufacturing a power semiconductor device A semiconductor power switch having an array of basic cells in which peripheral regions in the active drain region extend beside the perimeter of the base-drain junction, the peripheral regions being of higher dopant density than the rest of the second drain layer. ... | 09/21/2010 |
| 7750374 | Process for forming an electronic device including a transistor having a metal gate electrode An electronic device includes an n-channel transistor and a p-channel transistor. The p-channel transistor has a first gate electrode with a first work function and a first channel region including a semiconductor layer immediately adjacent to a semiconductor substr... | 07/06/2010 |
| 7737471 | Receiver circuit using nanotube-based switches and transistors Receiver circuits using nanotube-based switches and transistors. A receiver circuit includes a differential input having a first and second input link, a differential output having a first and second output link, and first and second switching elements in electrical... | 06/15/2010 |
| 7687829 | Stressed field effect transistors on hybrid orientation substrate A semiconductor structure having improved carrier mobility is provided. The semiconductor structures includes a hybrid oriented semiconductor substrate having at least two planar surfaces of different crystallographic orientation, and at least one CMOS device locate... | 03/30/2010 |
| 7679106 | Semiconductor integrated circuit A semiconductor integrated circuit having a substantially rectangular standard cell divided by first borderlines opposed to other standard cells longitudinally adjacent to the standard cell and second borderlines opposed to other standard cells laterally adjacent to... | 03/16/2010 |
| 7675091 | Semiconductor wafer and method of fabricating the same Disclosed is a semiconductor wafer and method of fabricating the same. The semiconductor wafer is comprised of a semiconductor layer formed on an insulation layer on a base substrate. The semiconductor layer includes a surface region organized in a first crystallogr... | 03/09/2010 |
| 7663164 | Semiconductor device with reduced leakage protection diode A protection diode is used in a CMOS integrated circuit device to direct charged particles to benign locations and prevent damage to the device. The protection diode includes a well region of a first conductivity type formed in a surface of a semiconductor substrate... | 02/16/2010 |
| 7646041 | Non-volatile memory devices including vertical channels, methods of operating, and methods of fabricating the same A flash memory device can include a semiconductor fin protruding from a semiconductor substrate of a first conductive type to extend in one direction, a first doped layer and a second doped layer provided to an upper portion and a lower portion of the semiconductor ... | 01/12/2010 |
| 7638821 | Integrated circuit incorporating decoupling capacitor under power and ground lines A semiconductor device is composed of: an array of CMOS primitive cells provided in a circuit region; a power supply line extended along the array of the CMOS primitive cells and connected to the CMOS primitive cells; a ground line extended along the array of the CM... | 12/29/2009 |
| 7566923 | Isolated power domain core regions in platform ASICs A platform application specific integrated circuit (ASIC) including a base layer. The base layer generally comprises a predefined input/output (I/O) region and a predefined core region. The predefined input/output (I/O) region may comprise a plurality of pre-diffuse... | 07/28/2009 |
| 7518167 | Semiconductor device A semiconductor device includes: a p-type MIS transistor having a first gate electrode including silicon doped with p-type impurities; an n-type MIS transistor having a second gate electrode including silicon doped with n-type impurities; and a shared line which con... | 04/14/2009 |
| 7465972 | High performance CMOS device design A semiconductor device includes a gate, which comprises a gate electrode and a gate dielectric underlying the gate electrode, a spacer formed on a sidewall of the gate electrode and the gate dielectric, a buffer layer having a first portion underlying the gate diele... | 12/16/2008 |
| 7456446 | Semiconductor device A semiconductor device of the generation with the minimum processing dimensions of 90 nm, or later, wherein variation of processing dimensions of gate electrodes in a logic block and a power source noise are suppressed; wherein a gate electrode formed to have a comb... | 11/25/2008 |
| 7439105 | Metal gate with zirconium A gate electrode (202) for a transistor including a metal gate structure (207) containing zirconium and a polycrystalline silicon cap (209) located there over. The metal gate structure (207) is located over a gate dielectric (205).... | 10/21/2008 |
| 7439559 | SOI device with different crystallographic orientations A method of forming a memory cell having a trench capacitor and a vertical transistor in a semiconductor substrate includes a step of providing a bonded semiconductor wafer having a lower substrate with an [010] axis parallel to a first wafer axis and an upper semic... | 10/21/2008 |
| 7432554 | CMOS thin film transistor comprising common gate, logic device comprising the CMOS thin film transistor, and method of manufacturing the CMOS thin film transistor A complementary metal oxide semiconductor (CMOS) thin film transistor including a common gate, a logic device including the CMOS thin film transistor, and a method of manufacturing the CMOS thin film transistor are provided. In one embodiment, the CMOS thin film tra... | 10/07/2008 |
| 7429762 | Semiconductor device and method of fabricating the same A semiconductor device includes a semiconductor substrate, first and second CMOS inverter circuits formed on the semiconductor substrate and constituting an SRAM memory cell, each inverter circuit having input and output terminals, and first and second resistance el... | 09/30/2008 |
| 7423324 | Double-gate MOS transistor, double-gate CMOS transistor, and method for manufacturing the same In a double-gate MOS transistor, a substrate, an insulating layer, and a semiconductor layer are formed or laminated in that order, an opening extending to the insulating layer is formed in the semiconductor layer while leaving an island-shaped region, the island-sh... | 09/09/2008 |
| 7413944 | CMOS image sensor and method of manufacturing the same In a CMOS image sensor manufacturing process, heavily doped p type impurity ions (for example, B) are implanted in a dummy moat region when the heavily doped p type impurity ions is implanted in a PMOS transistor region, so that metal ion contamination is removed. A... | 08/19/2008 |
| 7411227 | CMOS silicide metal gate integration The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present inve... | 08/12/2008 |
| 7405436 | Stressed field effect transistors on hybrid orientation substrate A semiconductor structure having improved carrier mobility is provided. The semiconductor structures includes a hybrid oriented semiconductor substrate having at least two planar surfaces of different crystallographic orientation, and at least one CMOS device locate... | 07/29/2008 |
| 7402846 | Electrostatic discharge (ESD) protection structure and a circuit using the same An electrostatic discharge (ESD) protection structure is disclosed. The ESD protection structure includes an active device. The active device includes a plurality of drains. Each of the drains has a contact row and at least one body contact row. The at least one bod... | 07/22/2008 |
| 7402847 | Programmable logic circuit and method of using same A programmable logic circuit, including programmable memory element, suitable for microprocessor applications, and a method of using the circuit are disclosed. The programmable circuit includes at least one logic cell, columns and rows of wires coupled to the logic ... | 07/22/2008 |
| 7400004 | Isolation structures for preventing photons and carriers from reaching active areas and methods of formation Regions of an integrated circuit are isolated by a structure that includes at least one isolating trench on the periphery of an active area. The trench is deep, extending at least about 0.5 μm into the substrate. The isolating structure prevents photons and electro... | 07/15/2008 |
| 7397075 | Method and apparatus providing CMOS imager device pixel with transistor having lower threshold voltage than other imager device transistors A transistor of a pixel cell for use in a CMOS imager with a low threshold voltage of about 0.3 V to less than about 0.7 V is disclosed. The transistor is provided with high dosage source and drain regions around the gate electrode and with the halo implanted region... | 07/08/2008 |
| 7394156 | Semiconductor integrated circuit device and method of producing the same A semiconductor integrated circuit device has a plurality of CMOS-type base cells arranged on a semiconductor substrate and m wiring layers, and gate array type logic cells are composed of the base cells and the wiring layers. Wiring within and between the logic cel... | 07/01/2008 |
| 7391063 | Display device A display device has C-MOS p-Si TFTs which enable high integration by reducing spaces for P-MOS TFTs and N-MOS TFTs in a driving circuit or the like thereof. A self-aligned C-MOS process is adopted, which uses a half tone mask as an exposure mask for manufacturing t... | 06/24/2008 |
| 7388238 | Semiconductor integrated circuit device with reduced leakage current The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage cur... | 06/17/2008 |
