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| Number | Title | Issue Date |
| 8148754 | Low resistance integrated MOS structure The present invention is related to a metal-oxide semiconductor field-effect transistor (MOSFET) having a symmetrical layout such that the resistance between drains and sources is reduced, thereby reducing power dissipation. Drain pads, source pads, and gates are pl... | 04/03/2012 |
| 8138524 | Self-aligned method of forming a semiconductor memory array of floating memory cells with source side erase, and a memory array made thereby A method of forming an array of floating gate memory cells, and an array formed thereby, wherein each memory cell includes a substrate of semiconductor material having a first conductivity type, source and drain regions formed in the substrate, a block of conductive... | 03/20/2012 |
| 8101974 | Semiconductor device and manufacturing method thereof A semiconductor device subjected to an optical annealing process by radiation light whose principal wavelength is 1.5 μm or less includes a circuit pattern region formed on a semiconductor substrate, and a dummy pattern region formed separately from the circuit pat... | 01/24/2012 |
| 8080834 | Semiconductor integrated circuit having polysilicon members A semiconductor integrated circuit includes a substrate, an oxide layer formed on an upper surface of the substrate, a plurality of polysilicon members arranged at constant intervals in a matrix on an upper surface of the oxide layer and including at least one first... | 12/20/2011 |
| 8053812 | Contact in planar NROM technology A method for fabricating a non-volatile memory array includes placing contacts over bit lines in a self-aligned manner. The placing includes forming self-aligned contact holes bounded by a second insulating material resistant to the removal of a first insulating mat... | 11/08/2011 |
| 8039873 | Semiconductor device A semiconductor device includes a substrate including an element region having a polygonal shape defined by a plurality of edges, and an isolation region surrounding the element region, and a plurality of gate electrodes provided on the substrate, crossing the eleme... | 10/18/2011 |
| 8013361 | Semiconductor device and method for fabricating the same Gate electrodes 5A through 5F are formed to have the same geometry, and protruding parts of the gate electrodes 5A through 5F extend across an isolation region onto impurity diffusion regions. The gate electrode 5B and P-type impur... | 09/06/2011 |
| 8004014 | Semiconductor integrated circuit device having metal interconnect regions placed symmetrically with respect to a cell boundary A layout structure of a semiconductor integrated circuit is provided with which narrowing and breaking of metal interconnects near a cell boundary can be prevented without increasing the data amount and processing time for OPC. A cell A and a cell B are adjacent to ... | 08/23/2011 |
| 8004015 | Semiconductor memory device having L-shaped cell blocks arranged in diagonal direction intersecting the horizontal and vertical directions Semiconductor devices are provided including a plurality of L-shaped cell blocks each including, a cell array and a plurality of decoders disposed in horizontal and vertical directions of the cell array. The plurality of L-shaped cell blocks are oriented in a diagon... | 08/23/2011 |
| 7985988 | Semiconductor device having circuit blocks in a single crystal layer, and bumps on certain blocks A semiconductor device 20 formed on a semiconductor chip substrate 30 has a plurality of circuit blocks made up of circuits each containing at least a metal oxide semiconductor (MOS) transistor 36, the circuit blocks being covered on top with a ... | 07/26/2011 |
| 7982243 | Multiple gate transistor architecture providing an accessible inner source-drain node The present invention provides a multiple gate transistor architecture that provides an accessible inner source-drain (SD) node. The transistor architecture includes a source structure having multiple source fingers, which extend from a source bus, and a drain struc... | 07/19/2011 |
| 7939855 | Semiconductor device A semiconductor device includes a substrate, first, second, and third gate lines disposed over the substrate, the first and second gate lines defining a first trench with a first aspect ratio, the second and third gate lines defining a second trench with a second as... | 05/10/2011 |
| 7932542 | Method of fabricating an integrated circuit with stress enhancement A method of fabricating an integrated circuit including arranging a plurality of cells to form a desired floor plan of the integrated circuit, wherein each cell comprises at least one transistor, forming a plurality of circuit constituents from the plurality of cell... | 04/26/2011 |
| 7932543 | Wire structure and semiconductor device comprising the wire structure Provided are a wire structure and a semiconductor device having the wire structure. The wire structure includes a first wire that has a first region having a width of several to tens of nanometers and a second region having a width wider than that of the first regio... | 04/26/2011 |
| 7923756 | Metal oxide semiconductor (MOS) device comprising a buried region under drain A semiconductor device with a metal oxide semiconductor (MOS) type transistor structure, which is used for, e.g. a static random access memory (SRAM) type memory cell, includes a part that is vulnerable to soft errors. In the semiconductor device with the MOS type t... | 04/12/2011 |
| 7888705 | Methods for defining dynamic array section with manufacturing assurance halo and apparatus implementing the same A method is disclosed for defining a dynamic array section to be manufactured on a semiconductor chip. The method includes defining a peripheral boundary of the dynamic array section. The method also includes defining a manufacturing assurance halo outside the bound... | 02/15/2011 |
| 7868357 | Gate driver-on-array structure and display panel A gate driver-on-array structure for using in a display panel including first conductive patterns, semiconductor patterns, second conductive patterns, third conductive patterns, first electrode line, and first connectors is provided. The first conductive patterns, t... | 01/11/2011 |
| 7863651 | Using multiple coulomb islands to reduce voltage stress A substrate is levitated a first distance over a mother substrate when a first group of Coulomb islands are charged. A second group of Coulomb islands are charged and increase a separation to a second distance. When the magnitude of the potential of all Coulomb isla... | 01/04/2011 |
| 7847320 | Dense chevron non-planar field effect transistors and method Disclosed are embodiments of semiconductor structure and a method of forming the semiconductor structure that simultaneously maximizes device density and avoids contacted-gate pitch and fin pitch mismatch, when multiple parallel angled fins are formed within a limit... | 12/07/2010 |
| 7800134 | CMOS integrated circuit devices having stressed NMOS and PMOS channel regions therein Methods of forming CMOS integrated circuit devices include forming at least first, second and third transistors in a semiconductor substrate and then covering the transistors with one or more electrically insulating layers that impart a net stress (tensile or compre... | 09/21/2010 |
| 7795643 | Cell array of semiconductor memory device and a method of forming the same A cell array includes a semiconductor substrate including an active region comprising a first region, a second region, and a transition region, the second region being separated from the first region by the transition region, wherein a top surface of the second regi... | 09/14/2010 |
| 7786512 | Dense non-volatile memory array and method of fabrication A non-volatile memory array includes a multiplicity of memory cells, each of whose area is less than 4 F2 per cell (where F is a minimum feature size), and periphery elements to control the memory cells. The present invention also includes a non-volatile ... | 08/31/2010 |
| 7750372 | Gate driver-on-array structure and display panel A gate driver-on-array structure integrated in a display panel includes a bar-like conductive layer, a semiconductor layer, first conductive patterns, second conductive patterns, a first electrode line and a second electrode line. The bar-like conductive layer has a... | 07/06/2010 |
| 7732838 | Semiconductor device and manufacturing method thereof A semiconductor device is provided. The semiconductor device includes a first gate line, a second gate line, a first contact electrode, first dummy gates, a second gate pad, and a second contact electrode. The first gate line is formed on a semiconductor substrate a... | 06/08/2010 |
| 7728360 | Multiple-gate transistor structure A multiple-gate transistor structure which includes a substrate, source and drain islands formed in a portion of the substrate, a fin formed of a semi-conducting material that has a top surface and two sidewall surfaces, a gate dielectric layer overlying the fin, an... | 06/01/2010 |
| 7683403 | Spatially aware drive strength dependent die size independent combinatorial spare cell insertion manner and related system and method A design method for an integrated circuit adds spare cells in a System-on-Chip to allow for Engineering Change Orders (ECOs) to be performed at a later stage in the design. This method can be used to provide a second version of the chip having minimal alterations pe... | 03/23/2010 |
| 7683401 | Semiconductor device and method of fabricating thereof capable of reducing a shallow trench isolation stress influence by utilizing layout pattern designs Provided is a semiconductor device. The semiconductor device includes a semiconductor substrate, a plurality of contact metals, and a gate electrode. The semiconductor substrate has an active region and a dummy active region, and a plurality of contact metals are fo... | 03/23/2010 |
| 7683402 | Semiconductor device and manufacturing method thereof Semiconductor devices whose current characteristics can be prevented from varying even if a phase shift mask is used for patterning gate electrodes of MISFETs, and a manufacturing method thereof are disclosed. According to one aspect of the present invention, there ... | 03/23/2010 |
| 7633098 | Field-effect-transistor multiplexing/demultiplexing architectures This disclosure relates to field-effect-transistor (FET) multiplexing/demultiplexing architectures and methods for fabricating them. One of these FET multiplexing/demultiplexing architectures enables decoding of an array of tightly pitched conductive structures. Ano... | 12/15/2009 |
| 7586131 | Transistor array and active-matrix substrate A transistor array includes conductor lines, function lines, and transistors. Each of the conductor lines includes a core and a conductor layer that covers the core. Each of the function lines includes a core, at least the surface of which is electrically conductive... | 09/08/2009 |
| 7582921 | Semiconductor device and method for patterning In a masking pattern (a) for patterning word and data lines, length is changed between adjacent word lines so as to be shifted from each other at their tips, and furthermore, the tip of each word line is cut obliquely. It is thus possible to prevent the resist patte... | 09/01/2009 |
| 7538368 | Standard cell, standard cell library, and semiconductor integrated circuit with suppressed variation in characteristics In a standard cell, at least one of transistors on either side of a transistor having gate length different from that of the other transistors are set to be always in the OFF state. This prevents influence to the operation of the standard cell even with variation in... | 05/26/2009 |
| 7465970 | Common pass gate layout of a D flip flop A semiconductor layout includes a p substrate, a first semiconductor cell formed over the p substrate, and a second semiconductor cell formed over the p substrate adjacent to the first semiconductor cell. A total height of the first semiconductor cell and the second... | 12/16/2008 |
| 7439894 | Electronic apparatus for current source array and layout method thereof An electronic apparatus for current source array and the layout method thereof are provided. The current source array includes a low bit group and a plurality of high bit groups. The low bit group has a plurality of current source units and is disposed at a central ... | 10/21/2008 |
| 7436007 | Master slice type semiconductor integrated circuit device A plurality of terminals is formed in a basic cell. One terminal has first to fifth patterns. The first and second patterns are arranged to be spaced from each other. The third and fourth patterns are arranged to be spaced from each other, and are arranged so as to ... | 10/14/2008 |
| 7422945 | Cell based integrated circuit and unit cell architecture therefor In a unit cell, a first conductive type active region and a second conductive type active region are provided. Those two active regions extend in a first direction. Each of the active regions have first and second ends thereof. The first end of the second conductive... | 09/09/2008 |
| 7423324 | Double-gate MOS transistor, double-gate CMOS transistor, and method for manufacturing the same In a double-gate MOS transistor, a substrate, an insulating layer, and a semiconductor layer are formed or laminated in that order, an opening extending to the insulating layer is formed in the semiconductor layer while leaving an island-shaped region, the island-sh... | 09/09/2008 |
| 7402846 | Electrostatic discharge (ESD) protection structure and a circuit using the same An electrostatic discharge (ESD) protection structure is disclosed. The ESD protection structure includes an active device. The active device includes a plurality of drains. Each of the drains has a contact row and at least one body contact row. The at least one bod... | 07/22/2008 |
| 7402847 | Programmable logic circuit and method of using same A programmable logic circuit, including programmable memory element, suitable for microprocessor applications, and a method of using the circuit are disclosed. The programmable circuit includes at least one logic cell, columns and rows of wires coupled to the logic ... | 07/22/2008 |
| 7402851 | Phase changeable memory devices including nitrogen and/or silicon and methods for fabricating the same Phase-changeable memory devices and method of fabricating phase-changeable memory devices are provided that include a phase-changeable material pattern of a phase-changeable material that may include nitrogen atoms and/or silicon atoms. First and second electrodes a... | 07/22/2008 |
