Did You Know...
...that Charles Goodyear performed some of his experiments on rubber while in debtor's prison? He was there so often he referred to it as his "hotel". Chronically in debt because of poor business sense and ill health, Goodyear depended on the generosity of friends and family. Even after he unlocked the secret to vulcanizing rubber, he was unable to improve his financial situation. When he died, his estate was $200,000 in debt.
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| Number | Title | Issue Date |
| 7994541 | Semiconductor device and metal line fabrication method of the same Embodiments relate to a method for forming a wiring in a semiconductor device, that may include laminating a conductive layer for wiring formation on a semiconductor substrate, forming a photoresist layer pattern on the conductive layer, performing primary dry etchi... | 08/09/2011 |
| RE42423 | Contact method for thin silicon carbide epitaxial layer and semiconductor devices formed by those methods Provided is a process for forming a contact for a compound semiconductor device without electrically shorting the device. In one embodiment, a highly doped compound semiconductor material is electrically connected to a compound semiconductor material of the same con... | 06/07/2011 |
| 7935986 | Method for forming a bipolar transistor device with self-aligned raised extrinsic base Disclosed are embodiments of a method of fabricating a bipolar transistor with a self-aligned raised extrinsic base. In the method a dielectric pad is formed on a substrate with a minimum dimension capable of being produced using current state-of-the-are lithographi... | 05/03/2011 |
| 7932541 | High performance collector-up bipolar transistor Disclosed are embodiments of a hetero-junction bipolar transistor (HBT) structure and method of forming the structure that provides substantially lower collector-to-base parasitic capacitance and collector resistance, while also lowering or maintaining base-to-emitt... | 04/26/2011 |
| 7829917 | Layout for self-aligned emitter-base processing The present invention provides a layout for a self-aligned semiconductor device, comprising an emitter mesa structure having an emitter electrode, and a base region that is comprised of a base electrode, with the base electrode deposited along crystal planes of the ... | 11/09/2010 |
| 7825436 | Thin film electron source A thin film electron source comprising a substrate, a lower electrode formed on one main face of said substrate, an insulation layer formed in contact with said lower electrode and an upper electrode formed in contact with said insulation layer. The upper electrode ... | 11/02/2010 |
| 7821037 | Heterojunction bipolar transistor A heterojunction bipolar transistor includes a first conductivity type subcollector layer, a first collector layer containing a first conductivity type impurity, a third collector layer containing a higher concentration of the first conductivity type impurity than t... | 10/26/2010 |
| 7791108 | Nanowire tunneling transistor A transistor comprises a nanowire (22, 22′) having a source (24) and a drain (29) separated by an intrinsic or lowly doped region (26, 28). A potential barrier is formed at the interface of the intrinsic or lowly doped region (26, 28... | 09/07/2010 |
| 7728359 | Nitride semiconductor based bipolar transistor and the method of manufacture thereof In a nitride semiconductor based bipolar transistor, a contact layer formed so as to contact an emitter layer is composed of n-type InAlGaN quaternary mixed crystals, the emitter layer and the contact layer are selectively removed so that the barrier height with the... | 06/01/2010 |
| 7723754 | Ge photodetectors A phototransistor includes an emitter and a base that comprises Ge. A collector comprises Si. The base, emitter, and collector form at least one Si/Ge heterojunction allowing the unpinning of Fermi energy level (EF) of the phototransistor. ... | 05/25/2010 |
| 7642569 | Transistor structure with minimized parasitics and method of fabricating the same A transistor having minimized parasitics is provided including an emitter having a recessed extrinsic emitter portion atop an intrinsic emitter portion; a base including an intrinsic base portion in electrical contact with the intrinsic emitter portion and an extrin... | 01/05/2010 |
| 7638820 | Contact method for thin silicon carbide epitaxial layer and semiconductor devices formed by those methods Provided is a process for forming a contact for a compound semiconductor device without electrically shorting the device. In one embodiment, a highly doped compound semiconductor material is electrically connected to a compound semiconductor material of the, same co... | 12/29/2009 |
| 7619263 | Method of radiation generation and manipulation A method of managing radiation having a frequency in the terahertz and/or microwave regions. The method comprises providing a semiconducting device having a two-dimensional carrier gas. Plasma waves are generated in the carrier gas using a laser pulse. The frequency... | 11/17/2009 |
| 7615805 | Versatile system for optimizing current gain in bipolar transistor structures Disclosed are apparatus and methods for designing electrical contact for a bipolar emitter structure. The area of an emitter structure (106, 306, 400, 404) and the required current density throughput of an electrical contact structure (108, 308, 402, 406 | 11/10/2009 |
| 7573080 | Transient suppression semiconductor device The HBT-based transient suppression device contains a collector layer of a first conduction type, a base layer of a second conduction type, an emitter layer of the first conduction type, stacked in this order sequentially on a top side of a heavily doped substrate o... | 08/11/2009 |
| 7569872 | Bipolar transistors with low parasitic losses Bipolar junction transistors (BJTs) and single or double heterojunction bipolar transistors with low parasitics, and methods for making the same is presented. A transistor is fabricated such that the collector region underneath a base contact area is deactivated. Th... | 08/04/2009 |
| 7465969 | Bipolar transistor and method for fabricating the same A bipolar transistor includes a Si single crystalline layer serving as a collector, a single crystalline Si/SiGeC layer and a polycrystalline Si/SiGeC layer which are formed on the Si single crystalline layer, an oxide film having an emitter opening portion, an emit... | 12/16/2008 |
| 7462892 | Semiconductor device A semiconductor device includes an emitter layer: a base layer; and a collector layer, wherein the collector layer and the emitter layer each include a heavily doped thin sublayer having a high impurity concentration, and each of the heavily doped thin sublayers has... | 12/09/2008 |
| 7432539 | Imaging method utilizing thyristor-based pixel elements An improved imaging array (and corresponding method of operation) includes a plurality of heterojunction thyristor-based pixel elements disposed within resonant cavities formed on a substrate. Each thyristor-based pixel element includes complementary n-type and p-ty... | 10/07/2008 |
| 7388237 | Local collector implant structure for heterojunction bipolar transistors A bipolar transistor structure includes an intrinsic base layer formed over a collector layer, an emitter formed over the intrinsic base layer, and an extrinsic base layer formed over the intrinsic layer and adjacent the emitter. A ring shaped collector implant stru... | 06/17/2008 |
| 7372084 | Low power bipolar transistors with low parasitic losses Low power double heterojunction bipolar transistors with low parasitics, and methods for making the same is presented. A transistor is fabricated such that the collector region underneath a base contact area is deactivated. This results in a drastic reduction of the... | 05/13/2008 |
| 7368361 | Bipolar junction transistors and method of manufacturing the same A substrate has a collector region of a first conductivity type, and a base layer of a single crystalline structure and including impurities of a second conductivity type is located over the collector region. An emitter region is defined at least in part by impuriti... | 05/06/2008 |
| 7368764 | Heterojunction bipolar transistor and method to make a heterojunction bipolar transistor A heterojunction bipolar transistor and a method of making a heterojunction bipolar transistor. The heterojunction bipolar transistor includes: a regrown emitter region; an intrinsic base region forming a junction with the regrown emitter region; and an extrinsic ba... | 05/06/2008 |
| 7368765 | Bipolar transistors with low parasitic losses Bipolar junction transistors (BJTs) and single or double heterojunction bipolar transistors with low parasitics, and methods for making the same is presented. A transistor is fabricated such that the collector region underneath a base contact area is deactivated. Th... | 05/06/2008 |
| 7364977 | Heterojunction bipolar transistor and method of fabricating the same Disclosed are a heterojunction bipolar transistor and a method of fabricating the same. A first dielectric layer easily etched is deposited on the overall surface of a substrate before an isolation region is defined. The first dielectric layer and a sub-collector la... | 04/29/2008 |
| 7359888 | Molecular-junction-nanowire-crossbar-based neural network A method for configuring nanoscale neural network circuits using molecular-junction-nanowire crossbars, and nanoscale neural networks produced by this method. Summing of weighted inputs within a neural-network node is implemented using variable-resistance resistors ... | 04/15/2008 |
| 7323728 | Semiconductor device Disclosed is a semiconductor device including an n+-type semiconductor layer formed on a substrate, a first n-type semiconductor layer formed on the n+-type semiconductor layer, a p-type semiconductor layer formed on the first n-type semiconduc... | 01/29/2008 |
| 7317506 | Variable illumination source An apparatus and method for providing a variable illumination field for use in lithographic imaging for semiconductor manufacturing includes providing a an illumination system including a variable optical element having an array of addressable elements, each address... | 01/08/2008 |
| 7317215 | SiGe heterojunction bipolar transistor (HBT) A heterojunction bipolar transistor is formed in a semiconductor substrate of a first conductivity type including a collector region. A base region is formed on the substrate and an emitter region is formed over the base region. At least one of the collector, base a... | 01/08/2008 |
| 7304333 | Semiconductor device A heterojunction bipolar transistor, having a structure in which a subcollector layer of a first conductive type having a higher doping concentration than a collector layer, a collector layer of the first conductive type, a base layer of the second conductive type, ... | 12/04/2007 |
| 7301181 | Heterojunction bipolar transistor having an emitter layer made of a semiconductor material including aluminum The present invention aims at providing a heterojunction bipolar transistor having improved breakdown voltage on operation for high power output, and includes: a GaAs semiconductor substrate 100; an n+-type GaAs sub-collector layer 110; an n... | 11/27/2007 |
| 7297992 | Method and structure for integration of phosphorous emitter in an NPN device in a BiCMOS process According to one exemplary embodiment, a heterojunction bipolar transistor includes a base situated on a substrate. The heterojunction bipolar transistor can be an NPN silicon-germanium heterojunction bipolar transistor, for example. The heterojunction bipolar trans... | 11/20/2007 |
| 7297993 | Bipolar transistor and fabrication method of the same A bipolar transistor having a base electrode of an air bridge structure is simplified in structure and enhanced in the degree of freedom of a contact position of a base wiring line with the base electrode. The bipolar transistor has a semiconductor mesa portion havi... | 11/20/2007 |
| 7294869 | Silicon germanium emitter Disclosed are an improved hetero-junction bipolar transistor (HBT) structure and a method of forming the structure that incorporates a silicon-germanium emitter layer with a graded germanium profile. The graded germanium concentration creates a quasi-drift field in ... | 11/13/2007 |
| 7291898 | Selective and non-selective epitaxy for base integration in a BiCMOS process and related structure According to one exemplary embodiment, a bipolar transistor includes an active area situated between first and second isolation regions in a substrate. The bipolar transistor further includes an epitaxial extension layer situated on the active area, where the epitax... | 11/06/2007 |
| 7285830 | Lateral bipolar junction transistor in CMOS flow An improved lateral bipolar junction transistor and a method of forming such a lateral bipolar transistor without added mask in CMOS flow on a p-substrate are disclosed. The CMOS flow includes patterning and n-well implants; pattern and implant pocket implants for c... | 10/23/2007 |
| 7285806 | Semiconductor device having an active region formed from group III nitride The semiconductor device of this invention includes an active region formed from a group III nitride semiconductor grown on a substrate and an insulating oxide film formed in a peripheral portion of the active region by oxidizing the group III nitride semiconductor.... | 10/23/2007 |
| 7282997 | Thermal coupling device A micro-electronic power amplifier that defines a uniform thermal impedance includes an output stage including a single transistor array including a plurality of emitter leads and a single thermal coupling device that thermally couples together each of the emitter l... | 10/16/2007 |
| 7282425 | Structure and method of integrating compound and elemental semiconductors for high-performance CMOS A method for fabricating a semiconductor substrate includes epitaxially growing an elemental semiconductor layer on a compound semiconductor substrate. An insulating layer is deposited on top of the elemental semiconductor layer, so as to form a first substrate. The... | 10/16/2007 |
| 7271429 | Nitride semiconductor device In a nitride semiconductor device according to one embodiment of the invention, a p-type gallium nitride (GaN) layer electrically connected to a source electrode and extending and projecting to a drain electrode side with respect to a gate electrode is formed on an ... | 09/18/2007 |
