Class 257/190 - With lattice constant mismatch (e.g., with buffer layer to accommodate mismatch)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: Subject matter wherein at least one of the materials that
No. of patents: 728
Last issue date: 05/22/2012

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Number	Title	Issue Date
8183594	Laminar structure on a semiconductor substrate An object of the present invention is to provide a ferroelectric element having excellent properties, which includes a monocrystalline film of γ-Al2O3 formed as a buffer layer on a silicon substrate. The monocrystalline γ-Al2O film...	05/22/2012
8178898	GaN-based semiconductor element A GaN-based semiconductor element includes a substrate, a buffer layer formed on the substrate, including an electrically conductive portion, an epitaxial layer formed on the buffer layer, and a metal structure in ohmic contact with the electrically conductive porti...	05/15/2012
8154050	Semiconductor device with semiconductor epitaxial layers buried in source/drain regions, and fabrication method of the same A semiconductor device in which semiconductor epitaxial layers are embedded in the source/drain regions includes an element formation region formed in the major surface of a semiconductor substrate, a gate electrode formed on a part of the element formation region, ...	04/10/2012
8148750	Transistor device having asymmetric embedded strain elements and related manufacturing method Semiconductor transistor devices and related fabrication methods are provided. An exemplary transistor device includes a layer of semiconductor material having a channel region defined therein and a gate structure overlying the channel region. Recesses are formed in...	04/03/2012
8143647	Relaxed InGaN/AlGaN templates A relaxed InGaN template employs a GaN or InGaN nucleation layer grown at low temperatures on a conventional base layer (e.g., sapphire). The nucleation layer is typically very rough and multi-crystalline. A single-crystal InGaN buffer layer is then grown at normal ...	03/27/2012
8143646	Stacking fault and twin blocking barrier for integrating III-V on Si A stacking fault and twin blocking barrier for forming a III-V device layer on a silicon substrate and the method of manufacture is described. Embodiments of the present invention enable III-V InSb device layers with defect densities below 1×108 cm�...	03/27/2012
8129747	Semiconductor heterostructures having reduced dislocation pile-ups and related methods Dislocation pile-ups in compositionally graded semiconductor layers are reduced or eliminated, thereby leading to increased semiconductor device yield and manufacturability. This is accomplished by introducing a semiconductor layer having a plurality of threading di...	03/06/2012
8120063	Modulation-doped multi-gate devices Modulation-doped multi-gate devices are generally described. In one example, an apparatus includes a semiconductor substrate having a surface, one or more buffer films coupled to the surface of the semiconductor substrate, a first barrier film coupled to the one or ...	02/21/2012
8093625	Nitride semiconductor light emitting device and method for fabricating the same Disclosed is a nitride semiconductor light emitting device. The nitride semiconductor light emitting device comprises a buffer layer having a super-lattice layer on a silicon substrate, a first conductive clad layer on the buffer layer, an active layer on the first ...	01/10/2012
8084784	Semiconductor heterostructure and method for forming same The invention relates to a method for forming a semiconductor heterostructure by providing a substrate with a first in-plane lattice parameter a1, providing a buffer layer with a second in-plane lattice parameter a2 and providing a top layer ov...	12/27/2011
8080833	Thick pseudomorphic nitride epitaxial layers In various embodiments, a semiconductor device includes an aluminum nitride single-crystal substrate, a pseudomorphic strained layer disposed thereover that comprises at least one of AlN, GaN, InN, or an alloy thereof, and, disposed over the strained layer, a semico...	12/20/2011
8067787	Semiconductor electronic device A semiconductor electronic device comprises a substrate; a buffer layer formed on the substrate, the buffer layer including not less than two layers of composite layer in which a first semiconductor layer formed of a nitride-based compound semiconductor layer having...	11/29/2011
8053811	Group 3-5 nitride semiconductor multilayer substrate, method for manufacturing group 3-5 nitride semiconductor free-standing subtrate, and semiconductor element A group 3-5 nitride semiconductor multilayer substrate (1) and a method for manufacturing such substrate are provided. A semiconductor layer (12) is formed on a base substrate (11), and a mask (13) is formed on the semiconductor layer (	11/08/2011
8053810	Structures having lattice-mismatched single-crystalline semiconductor layers on the same lithographic level and methods of manufacturing the same A semiconductor substrate containing a single crystalline group IV semiconductor is provided. A single crystalline lattice mismatched group IV semiconductor alloy layer is epitaxially grown on a portion of the semiconductor layer, while another portion of the semico...	11/08/2011
8039869	Gallium nitride device substrate containing a lattice parameter altering element A gallium nitride device substrate comprises a layer of gallium nitride containing an additional lattice parameter altering element located over a substitute substrate. ...	10/18/2011
8004010	Semiconductor device and a method of manufacturing the same In a semiconductor device with a shared contact, a gate electrode is formed via a gate insulating film on a semiconductor substrate and a sidewall insulating film is formed on both side faces of the gate electrode. At least one of the surface parts of the semiconduc...	08/23/2011
7994538	Semiconductor device and method of manufacturing the same A semiconductor device to which a stress technique is applied and in which a leakage current caused by silicidation can be suppressed. A gate electrode is formed over an element region defined by an isolation region formed in a semiconductor substrate with a gate in...	08/09/2011
7994539	Light emitting diode having algan buffer layer and method of fabricating the same The present invention relates to a light emitting diode having an AlxGa1−xN buffer layer and a method of fabricating the same, and more particularly, to a light emitting diode having an AlxGa1−xN buffer layer, wherein ...	08/09/2011
7985984	III-nitride semiconductor field effect transistor Provided is a semiconductor device that can reduce the contact resistance, has a small current collapse, and can improve the pinch-off characteristic upon a high-frequency operation. A field effect transistor using a wurtzite (having (0001) as the main plane) type I...	07/26/2011
7977706	Tri-gate field-effect transistors formed by aspect ratio trapping Semiconductor structures include a trench formed proximate a substrate including a first semiconductor material. A crystalline material including a second semiconductor material lattice mismatched to the first semiconductor material is formed in the trench. Process ...	07/12/2011
7973336	Released freestanding strained heterojunction structures Growth of multilayer films is carried out in a manner which allows close control of the strain in the grown layers and complete release of the grown films to allow mounting of the released multilayer structures on selected substrates. A layer of material, such as si...	07/05/2011
7973337	Source/drain strained layers A semiconductor device and method of manufacture thereof wherein a PMOS source/drain region of a transistor within the substrate includes a first strained layer in the PMOS source/drain region and a first capping layer in contact with the first strained layer. Furth...	07/05/2011
7968910	Complementary field effect transistors having embedded silicon source and drain regions A method is provided of fabricating complementary stressed semiconductor devices, e.g., an NFET having a tensile stressed channel and a PFET having a compressive stressed channel. In such method, a first semiconductor region having a lattice constant larger than sil...	06/28/2011
7968911	Relaxation of a strained layer using a molten layer A crystalline wafer comprising of a support substrate, a first layer and an interface layer. The first layer is of a first material in a relaxed state having a lattice parameter that is substantially equal to the nominal lattice parameter of the first material. The ...	06/28/2011
7964894	Integrated circuit system employing stress memorization transfer An integrated circuit system that includes: a substrate including a source/drain region defined by a spacer; a gate over the substrate; a gate dielectric between the gate and the substrate; a recrystallized region within the gate and the source/drain region; and a c...	06/21/2011
7948008	Floating body field-effect transistors, and methods of forming floating body field-effect transistors In one embodiment, a floating body field-effect transistor includes a pair of source/drain regions having a floating body channel region received therebetween. The source/drain regions and the floating body channel region are received over an insulator. A gate elect...	05/24/2011
7948009	Nitride semiconductor epitaxial wafer and nitride semiconductor device A nitride semiconductor epitaxial wafer includes a growth substrate including a surface for growing a nitride semiconductor thereon, a first structure layer formed on the growth substrate, a dislocation propagation direction changing layer formed on the first struct...	05/24/2011
7948010	Dual seed semiconductor photodetectors Dual seed semiconductor photodetectors and methods to fabricate thereof are described. A dual seed semiconductor photodetector is formed directly on an insulating layer on a substrate. The dual seed semiconductor photodetector includes an optical layer formed on a d...	05/24/2011
7939852	Transistor device having asymmetric embedded strain elements and related manufacturing method Semiconductor transistor devices and related fabrication methods are provided. An exemplary transistor device includes a layer of semiconductor material having a channel region defined therein and a gate structure overlying the channel region. Recesses are formed in...	05/10/2011
7928474	Forming embedded dielectric layers adjacent to sidewalls of shallow trench isolation regions A semiconductor structure is provided. The semiconductor structure includes a semiconductor substrate; an insulating region extending from substantially a top surface of the semiconductor substrate into the semiconductor substrate; an embedded dielectric spacer adja...	04/19/2011
7915640	Heterojunction semiconductor device and method of manufacturing A metamorphic buffer layer is formed on a semi-insulating substrate by an epitaxial growth method, a collector layer, a base layer, an emitter layer and an emitter cap layer are sequentially laminated on the metamorphic buffer layer, and a collector electrode is pro...	03/29/2011
7906798	Semiconductor device having buffer layer between sidewall insulating film and semiconductor substrate A semiconductor device includes an NMOS transistor and a PMOS transistor. The NMOS transistor includes a channel area formed in a silicon substrate, a gate electrode formed on a gate insulating film in correspondence with the channel area, and a source area and a dr...	03/15/2011
7859013	Metal oxide field effect transistor with a sharp halo Disclosed are embodiments of a MOSFET with defined halos that are bound to defined source/drain extensions and a method of forming the MOSFET. A semiconductor layer is etched to form recesses that undercut a gate dielectric layer. A low energy implant forms halos. T...	12/28/2010
7851824	Light emitting device having a composition modulation layer of unequal amounts of at least two elements between an n-type contact layer and a transparent electrode A light emitting device includes: a light emitting layer; an n-type contact layer made of a compound provided on the light emitting layer; a composition modulation layer provided on the n-type contact layer; and a transparent electrode provided on the composition mo...	12/14/2010
7838903	Compound semiconductor device and the fabricating method of the same A GaN layer functions as an electron transit layer and is formed to exhibit, at least at a portion thereof, A/B ratio of 0.2 or less obtained by a photoluminescence measurement, where “A” is the light-emission intensity in the 500-600 nm band, and “B” is the...	11/23/2010
7825432	Nitride semiconductor structures with interlayer structures A semiconductor structure includes a first layer of a nitride semiconductor material, a substantially unstrained nitride interlayer on the first layer of nitride semiconductor material, and a second layer of a nitride semiconductor material on the nitride interlayer...	11/02/2010
7791105	Device structures for a high voltage junction field effect transistor manufactured using a hybrid orientation technology wafer and design structures for a high voltage integrated circuit Device structures for a high voltage junction field effect transistor and design structures for a high voltage integrated circuit. The device structure is manufactured using a hybrid orientation technology wafer with a first semiconductor layer with a first crystall...	09/07/2010
7781800	Embedded silicon germanium using a double buried oxide silicon-on-insulator wafer Disclosed is a p-type field effect transistor (pFET) structure and method of forming the pFET. The pFET comprises embedded silicon germanium in the source/drain regions to increase longitudinal stress on the p-channel and, thereby, enhance transistor performance. In...	08/24/2010
7781799	Source/drain strained layers A semiconductor device and method of manufacture thereof wherein a PMOS source/drain region of a transistor within the substrate includes a first strained layer in the PMOS source/drain region and a first capping layer in contact with the first strained layer. Furth...	08/24/2010
7777250	Lattice-mismatched semiconductor structures and related methods for device fabrication Lattice-mismatched materials having configurations that trap defects within sidewall-containing structures. ...	08/17/2010

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Class 257/190 - With lattice constant mismatch (e.g., with buffer layer to accommodate mismatch)