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| Number | Title | Issue Date |
| 8178863 | Lateral collection architecture for SLS detectors Lateral collection architecture for a photodetector is achieved by depositing electrically conducting SLS layers onto a planar substrate and diffusing dopants of a carrier type opposite that of the layers through the layers at selected regions to disorder the superl... | 05/15/2012 |
| 8164085 | Semiconductor device and production method thereof A method of fabricating a semiconductor device is disclosed that is able to suppress a short channel effect and improve carrier mobility. In the method, trenches are formed in a silicon substrate corresponding to a source region and a drain region. When epitaxially ... | 04/24/2012 |
| 8115194 | Semiconductor device capable of providing identical strains to each channel region of the transistors A semiconductor device including transistors and strain layers is provided. Each transistor includes a source region and a drain region on a substrate and a gate structure on a channel region between the source region and the drain region. Lengths of the channel reg... | 02/14/2012 |
| 8106380 | Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semi... | 01/31/2012 |
| 8063397 | Semiconductor light-emitting structure and graded-composition substrate providing yellow-green light emission Semiconductor light-emitting structures are shown on engineered substrates having a graded composition. The composition of the substrate may be graded to achieve a lattice constant on which a yellow-green light-emitting semiconductor material may be disposed. In som... | 11/22/2011 |
| 7868317 | MOS devices with partial stressor channel A semiconductor structure includes a semiconductor substrate having a first lattice constant; a gate dielectric on the semiconductor substrate; a gate electrode on the semiconductor substrate; and a stressor having at least a portion in the semiconductor substrate a... | 01/11/2011 |
| 7847281 | Semiconductor device with strain in channel region and its manufacture method A first film made of SiGe is formed over a support substrate whose surface layer is made of Si. A gate electrode is formed over a partial area of the first film, and source and drain regions are formed in the surface layer of the support substrate on both sides of t... | 12/07/2010 |
| 7812340 | Strained-silicon-on-insulator single-and double-gate MOSFET and method for forming the same A method of forming a semiconductor structure (and the resulting structure), includes straining a free-standing semiconductor, and fixing the strained, free-standing semiconductor to a substrate. ... | 10/12/2010 |
| 7755079 | Strained-layer superlattice focal plane array having a planar structure An infrared focal plane array (FPA) is disclosed which utilizes a strained-layer superlattice (SLS) formed of alternating layers of InAs and InxGa1−xSb with 0≦x≦0.5 epitaxially grown on a GaSb substrate. The FPA avoids the use of a mesa s... | 07/13/2010 |
| 7723720 | Methods and articles incorporating local stress for performance improvement of strained semiconductor devices A packaged semiconductor device (450) includes a semiconductor chip (400) having at least one selectively thinned substrate (cavity) region (410). A package (460) is provided for mounting, enclosing and electrically connecting the chip ( | 05/25/2010 |
| 7714318 | Electronic device including a transistor structure having an active region adjacent to a stressor layer An electronic device can include a transistor structure of a first conductivity type, a field isolation region, and a layer of a first stress type overlying the field isolation region. For example, the transistor structure may be a p-channel transistor structure and... | 05/11/2010 |
| 7629603 | Strain-inducing semiconductor regions A method to form a strain-inducing semiconductor region comprising three or more species of charge-neutral lattice-forming atoms is described. In one embodiment, formation of a strain-inducing semiconductor region, comprising three or more species of charge-neutral ... | 12/08/2009 |
| 7595499 | Method and system for fabricating strained layers for the manufacture of integrated circuits A method for forming a strained layer of semiconductor material, e.g., silicon, germanium, Group III/V, silicon germanium alloy. The method includes providing a non-deformable surface region having a first predetermined radius of curvature, which is defined by R(... | 09/29/2009 |
| 7554110 | MOS devices with partial stressor channel A semiconductor structure includes a semiconductor substrate having a first lattice constant; a gate dielectric on the semiconductor substrate; a gate electrode on the semiconductor substrate; and a stressor having at least a portion in the semiconductor substrate a... | 06/30/2009 |
| 7538339 | Scalable strained FET device and method of fabricating the same An integrated circuit including pairs of strained complementary CMOS field-effect devices consisting of n-FET and p-FET transistors on a substrate. The n-FET is provided with a compressive dielectric stressor, while the p-FET is provided with a tensile stressed diel... | 05/26/2009 |
| 7443561 | Deep quantum well electro-absorption modulator Double well structures in electro-absorption modulators are created in quantum well active regions by embedding deep ultra thin quantum wells. The perturbation introduced by the embedded, deep ultra thin quantum well centered within a conventional quantum well lower... | 10/28/2008 |
| 7436026 | Semiconductor device comprising a superlattice channel vertically stepped above source and drain regions A semiconductor device may include a semiconductor substrate and at least one metal oxide semiconductor field-effect transistor (MOSFET). The at least one MOSFET may include spaced apart source and drain regions in the semiconductor substrate, and a superlattice cha... | 10/14/2008 |
| 7429748 | High speed GE channel heterostructures for field effect devices A method and a layered heterostructure for forming high mobility Ge channel field effect transistors is described incorporating a plurality of semiconductor layers on a semiconductor substrate, and a channel structure of a compressively strained epitaxial Ge layer h... | 09/30/2008 |
| 7427554 | Manufacturing strained silicon substrates using a backing material A method for forming a strained silicon layer of semiconductor material. The method includes providing a deformable surface region having a first predetermined radius of curvature, which is defined by R(1) and is defined normal to the surface region. A backin... | 09/23/2008 |
| 7423283 | Strain-silicon CMOS using etch-stop layer and method of manufacture Recesses are formed in the drain and source regions of an MOS transistor. An ohmic contact layer is formed in the recesses, and a stressed silicon-nitride layer is formed over the ohmic contact layer. The recesses allow the stressed silicon nitride layer to provide ... | 09/09/2008 |
| 7420201 | Strained-semiconductor-on-insulator device structures with elevated source/drain regions The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication. ... | 09/02/2008 |
| 7420202 | Electronic device including a transistor structure having an active region adjacent to a stressor layer and a process for forming the electronic device An electronic device can include a transistor structure of a first conductivity type, a field isolation region, and a layer of a first stress type overlying the field isolation region. For example, the transistor structure may be a p-channel transistor structure and... | 09/02/2008 |
| 7413970 | Process of forming an electronic device including a semiconductor fin An electronic device can include a semiconductor fin overlying an insulating layer. The electronic device can also include a semiconductor layer overlying the semiconductor fin. The semiconductor layer can have a first portion and a second portion that are spaced-ap... | 08/19/2008 |
| 7414259 | Strained germanium-on-insulator device structures The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication. ... | 08/19/2008 |
| 7415185 | Buried-waveguide-type light receiving element and manufacturing method thereof A buried-waveguide light detecting element includes an n-type cladding layer on a Fe-InP substrate, a waveguide on a portion of the n-type cladding layer, and in which an n-type light guide layer, an i-light guide layer having a refractive index equal to or higher t... | 08/19/2008 |
| 7405422 | Epitaxial and polycrystalline growth of SiGeCand SiCalloy layers on Si by UHV-CVD A method and apparatus for depositing single crystal, epitaxial films of silicon carbon and silicon germanium carbon on a plurality of substrates in a hot wall, isothermal UHV-CVD system is described. In particular, a multiple wafer low temperature growth technique ... | 07/29/2008 |
| 7391047 | System for forming a strained layer of semiconductor material A method for forming a strained layer of semiconductor material, e.g., silicon, germanium, Group III/V, silicon germanium alloy. The method includes providing a non-deformable surface region having a first predetermined radius of curvature, which is defined by R(1) ... | 06/24/2008 |
| 7375368 | Superlattice for fabricating nanowires This disclosure relates to a system and method for creating nanowires. A nanowire can be created by exposing layers of material in a superlattice and dissolving and transferring material from edges of the exposed layers onto a substrate. The nanowire can also be cre... | 05/20/2008 |
| 7371628 | Method for fabricating semiconductor device A method for fabricating a semiconductor device is provided. The method mainly involves steps of forming at least one first patterned high stress layer below a silicon substrate, then forming a semiconductor device onto the substrate, and forming at least one second... | 05/13/2008 |
| 7368764 | Heterojunction bipolar transistor and method to make a heterojunction bipolar transistor A heterojunction bipolar transistor and a method of making a heterojunction bipolar transistor. The heterojunction bipolar transistor includes: a regrown emitter region; an intrinsic base region forming a junction with the regrown emitter region; and an extrinsic ba... | 05/06/2008 |
| 7368308 | Methods of fabricating semiconductor heterostructures Dislocation pile-ups in compositionally graded semiconductor layers are reduced or eliminated, thereby leading to increased semiconductor device yield and manufacturability. This is accomplished by introducing a semiconductor layer having a plurality of threading di... | 05/06/2008 |
| 7368766 | Semiconductor light emitting element and method for fabricating the same The semiconductor laser of this invention includes an active layer formed in a c-axis direction, wherein the active layer is made of a hexagonal-system compound semiconductor, and anisotropic strain is generated in a c plane of the active layer. ... | 05/06/2008 |
| 7368334 | Silicon-on-insulator chip with multiple crystal orientations A silicon-on-insulator chip includes an insulator layer, typically formed over a substrate. A first silicon island with a surface of a first crystal orientation overlies the insulator layer and a second silicon island with a surface of a second crystal orientation a... | 05/06/2008 |
| 7365357 | Strain inducing multi-layer cap A strained transistor includes a silicon transistor, an encapsulating layer of silicon insulating material with an outer surface, and a stress inducing multilayer cap deposited on the outer surface of the encapsulating layer with at least two layers including a laye... | 04/29/2008 |
| 7365369 | Nitride semiconductor device A nitride semiconductor device used chiefly as an LD and an LED element. In order to improve the output and to decrease Vf, the device is given either a three-layer structure in which a nitride semiconductor layer doped with n-type impurities serving as an n-type co... | 04/29/2008 |
| 7358523 | Method and structure for deep well structures for long wavelength active regions Subwells are added to quantum wells of light emitting semiconductor structures to shift their emission wavelengths to longer wavelengths. Typical applications of the invention are to InGaAs, InGaAsSb, InP and GaN material systems, for example. ... | 04/15/2008 |
| 7357018 | Method for performing a measurement inside a specimen using an insertable nanoscale FET probe A measurement inside a specimen is performed by providing a nanoscale FET probe comprising a cantilever element and a nanowire extending from the cantilever element. The nanowire is electrically connected to the cantilever element at at least one of the ends of the ... | 04/15/2008 |
| 7352008 | Heterostructure with rear-face donor doping The present invention relates to a field effect transistor having heterostructure with a buffer layer or substrate. A channel is arranged on the buffer layer or on the substrate, and a capping layer is arranged on the channel. The channel consists of a piezopolar ma... | 04/01/2008 |
| 7351994 | Noble high-k device At least one high-k device, and a method for forming the at least one high-k device, comprising the following. A structure having a strained substrate formed thereover. The strained substrate comprising at least an uppermost strained-Si epi layer. At least one diele... | 04/01/2008 |
| 7348201 | Creation of anisotropic strain in semiconductor quantum well Methods and devices for creating an anisotropic strain in a semiconductor quantum well structure to induce anisotropy thereof are disclosed herein. Initially, a substrate is provided, and a quantum well structure formed upon the substrate. A first crystalline layer ... | 03/25/2008 |
