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| Number | Title | Issue Date |
| 7414262 | Electronic devices and methods for forming the same Electronic devices, such as those having a flexible substrate and printed material on the flexible substrate. In one embodiment, the printed material and substrate are part of an electronic device having at least three terminals, wherein the electronic device has a ... | 08/19/2008 |
| 7348630 | Semiconductor device for high frequency uses and manufacturing method of the same The semiconductor device has a semiconductor substrate, gate electrodes formed above the semiconductor substrate, and a pair of impurity diffusion layers formed in a surface layer of the semiconductor substrate at both sides of each of the gate electrodes. The semic... | 03/25/2008 |
| 7345296 | Nanotube transistor and rectifying devices Single-walled carbon nanotube transistor and rectifying devices, and associated methods of making such devices include a porous structure for the single-walled carbon nanotubes. The porous structure may be anodized aluminum oxide or another material. Electrodes for ... | 03/18/2008 |
| 7321251 | Bias circuit and method of producing semiconductor device A bias circuit able to keep a bias current constant even if a threshold voltage of a transistor changes, provided with a resistance element connected between a bias voltage supply line and a gate and changing in resistance value linked with the threshold value of th... | 01/22/2008 |
| 7315052 | Power FET with embedded body pickup A power transistor formed on a semiconductor substrate and including a lateral array of polysilicon lines separated by alternating source and drain regions includes one or more body contact diffusion regions formed in the source regions where each body contact diffu... | 01/01/2008 |
| 7262485 | Substrate for growing electro-optical single crystal thin film and method of manufacturing the same A substrate 1 for growing an electro-optical single crystal thin film in which two or more layers of buffer layers 3, 4, and 5 for buffering lattice mismatch between Si and BTO are formed on an Si (001) substrate 2 is provided as a substr... | 08/28/2007 |
| 7227197 | Semiconductor high-voltage devices A semiconductor high-voltage device comprising a voltage sustaining layer between a n+-region and a p+-region is provided, which is a uniformly doped n(or p)-layer containing a plurality of floating p (or n)-islands. The effect of the floating islands is to absorb a... | 06/05/2007 |
| 7199404 | Semiconductor substrate and semiconductor device using the same A semiconductor substrate used for fabricating vertical devices, such as vertical MOSFET, capable of maintaining low ON-stage resistance and of ensuring a necessary level of OFF-stage breakdown voltage is provided. A heavily-doped arsenic layer of 0.5 to 3.0 μm thi... | 04/03/2007 |
| 7029956 | Memory system capable of operating at high temperatures and method for fabricating the same A memory system having a plurality of T-RAM cells arranged in an array is presented where each T-RAM cell has dual vertical devices and is fabricated over a SiC substrate. Each T-RAM cell has a vertical thyristor and a vertical transfer gate. The top surface of each... | 04/18/2006 |
| 6936867 | Semiconductor high-voltage devices A semiconductor high-voltage device comprising a voltage sustaining layer between a n+-region and a p+-region is provided, which is a uniformly doped n(or p)-layer containing a plurality of floating p (or n)-islands. The effect of the floating islands is to absorb a... | 08/30/2005 |
| 6924177 | Method for producing a thyristor A thyristor having a first zone, a second zone, a third zone, and a fourth zone. At least one control electrode is connected to the second and/or third zone. In order to reduce the static and dynamic power loss in a symmetrical thyristor, it is proposed that a field... | 08/02/2005 |
| 6888177 | Increased base-emitter capacitance A thyristor-based semiconductor device exhibits a relatively increased base-emitter capacitance. According to an example embodiment of the present invention, the junction area between a base region and an adjacent emitter region of a thyristor is increased, relative... | 05/03/2005 |
| 6867083 | Method of forming a body contact of a transistor and structure therefor A transistor (10, 30, 60) is formed to have a body contact (16, 36, 69) that has a minimal contact to the sides of the source region (14, 34, 63). This increases the density and reduces on-resistance of the transistor (10, 30, 60). ... | 03/15/2005 |
| 6858887 | BJT device configuration and fabrication method with reduced emitter width A BJT device configuration includes an emitter finger and via arrangement which reduces emitter finger width, and is particularly suitable for use with compound semiconductor-based devices. Each emitter finger includes a cross-shaped metal contact which provides an ... | 02/22/2005 |
| 6825110 | Method for fabricating semiconductor component with an optimized thickness In a method for fabricating a semiconductor component with a cathode and an anode from a wafer, the wafer is first provided with a stop zone, thereupon treated on the cathode side and only then reduced in its thickness, so that all that remains of the stop zone is a... | 11/30/2004 |
| 6734497 | Insulated gate bipolar transistor, semiconductor device, method of manufacturing insulated-gate bipolar transistor, and method of manufacturing semiconductor device An insulated gate bipolar transistor, a semiconductor device using such a transistor, and manufacturing methods of these. The transistor, device, and method eliminate the necessity of connection to a freewheel diode used for bypassing a circulating current. In the t... | 05/11/2004 |
| 6635906 | Voltage sustaining layer with opposite-doped islands for semi-conductor power devices A semiconductor high-voltage device comprising a voltage sustaining layer between a n+ -region and a p+ -region is provided, which is a uniformly doped n(or p)-layer containing a plurality of floating p(or n)-islands. The effect of t... | 10/21/2003 |
| 6583024 | High resistivity silicon wafer with thick epitaxial layer and method of producing same A silicon wafer having a thick, high-resistivity epitaxially grown layer and a method of depositing a thick, high-resistivity epitaxial layer upon a silicon substrate, such method accomplished by: a) providing a silicon wafer substrate and b) depositing a... | 06/24/2003 |
| 6525346 | Semiconductor device and its manufacturing method capable of reducing low frequency noise In a semiconductor device, a first semiconductor layer is formed on a semiconductor substrate. A second semiconductor layer is formed on a part of the first semiconductor layer, and a third semiconductor layer is formed on a part of the second semiconduct... | 02/25/2003 |
| 6465283 | Structure and fabrication method using latch-up implantation for improving latch-up immunity in CMOS fabrication process A structure and fabrication method using latch-up implantation to improve latch-up immunity in CMOS circuit. The impedance of parasitic SCR conducting path is raised by performing an ion-implantation process on a cathode and an anode of a parasitic SCR wh... | 10/15/2002 |
| 6452219 | Insulated gate bipolar transistor and method of fabricating the same An IGBT having a buffer layer for shortening the turn-off time and for preventing the latching up is improved. The buffer layer of the present invention is not bare at the edge of a diced cross-section of the IGBT chip. According to this construction, a w... | 09/17/2002 |
| 6281546 | Insulated gate field effect transistor and manufacturing method of the same A wide high concentration P+ type region is formed on the surface of an N- type epitaxial layer formed on a P type substrate in the vicinity of the edge portion of a cell region in which a transistor device is formed. As a result, ho... | 08/28/2001 |
| 6255672 | Semiconductor device A semiconductor device includes a pair of semiconductor switching elements and a board. Each semiconductor switching element has positive and control electrodes formed on one surface and a negative electrode formed on the other surface. The positive and c... | 07/03/2001 |
| 5977569 | Bidirectional lateral insulated gate bipolar transistor having increased voltage blocking capability A bidirectional lateral insulated gate bipolar transistor (IGBT) includes two gate electrodes. The IGBT can conduct current in two directions. The IGBT relies on a double RESURF structure to provide high voltage blocking in both directions. The IGBT is sy... | 11/02/1999 |
| 5917204 | Insulated gate bipolar transistor with reduced electric fields AN IGBT including a collector positioned on one surface of a substrate and a doped structure having a buried region therein positioned on the other surface of the substrate. The buried region defining a drift region in the doped structure extending vertic... | 06/29/1999 |
| 5757035 | Semiconductor device In a surface of a silicon substrate of one conductivity type, there are formed a plurality of depressions or recesses, gate regions of opposite conductivity type are formed at bottoms of respective recesses, gate electrodes are provided on respective gate... | 05/26/1998 |
| 5753943 | Insulated gate type field effect transistor and method of manufacturing the same In an insulated gate type field effect transistor and a manufacturing method of the same, a diffusion region is formed in a semiconductor substrate under an oxidizing atmosphere by thermal diffusion, and a first conductivity type semiconductor layer is fo... | 05/19/1998 |
| 5701023 | Insulated gate semiconductor device typically having subsurface-peaked portion of body region for improved ruggedness An insulated gate semiconductor device contains a common drain and a plurality of cells, each having a body region and a source. In each cell, the body region contains a channel region extending between the common drain and the source. The body region fur... | 12/23/1997 |
| 5644149 | Anode-side short structure for asymmetric thyristors A thyristor according to the invention comprises a layer sequence containing an n-type emitter layer (4), a p-type base layer (5), an n-type base layer (6) and a p-type emitter layer (7) in a semiconductor substrate (3) between an anode (1) and a cathode ... | 07/01/1997 |
| 5631483 | Power device integrated structure with low saturation voltage A power device integrated structure includes a semiconductor substrate of a first conductivity type, a semiconductor layer of a second conductivity type superimposed over the substrate, a plurality of first doped regions of the first conductivity type for... | 05/20/1997 |
| 5591991 | Semiconductor device and method of manufacturing the same After selectively forming P+ -type gate regions 14 in the upper surface of a first N- -type semiconductor substrate 10, gate electrodes 30 are selectively formed on the P+ -type gate regions. A P+ -type layer 12... | 01/07/1997 |
| 5528058 | IGBT device with platinum lifetime control and reduced gaw For IGBT, MCT or like devices, the substrate is formed with P+, N+ and N- layers and PN diffusions to define body and source regions in the N-layer and a MOS-gated channel at the upper surface. The N-layer is sized and doped (~1014 /cm3 | 06/18/1996 |
| 5466951 | Controllable power semiconductor element with buffer zone and method for the manufacture thereof Controllable power semiconductor components such as, for example, IGBTs and thyristors are provided, which, compared to known components, have a relatively lightly doped n-buffer zone, a relatively flat p-emitter, and an n-base having a comparatively long... | 11/14/1995 |
| 5463231 | Method of operating thyristor with insulated gates A thyristor with insulated gates includes turn-off and turn-on MOSFETs. The turn-on MOSFET has a turn-on gate employing a p-type base as a channel and extending over an n-type base and an n-type emitter. The turn-off MOSFET has n-type drain and source lay... | 10/31/1995 |
| 5391898 | Insulated gate bipolar transistor having high short-circuit and latch-up withstandability An IGBT has an emitter bypass structure. The interval D between N emitter regions is adapted to be larger than two times of a channel length L in order to effectively decrease a channel width to effectively decrease a saturation current. A high concentrat... | 02/21/1995 |
| 5360983 | Insulated gate bipolar transistor having a specific buffer layer resistance An n+ buffer layer, that is located between an n- base layer and a p+ substrate, has a resistivity in the range of 0.005-0.03 Ωcm and a thickness not more than 10μm. Further, the base layer has an impurity concentration... | 11/01/1994 |
| 5357120 | Compound semiconductor device and electric power converting apparatus using such device A compound semiconductor device is provided which includes a thyristor region constructed by four continuous layers of p-n-p-n and an MOSFET region which is formed in the intermediate n layer of the thyristor region so as to be away from the intermediate ... | 10/18/1994 |
| 5326993 | Insulated gate bipolar transistor An insulated gate bipolar transistor employs a semiconductor substrate constructed by putting a high impurity density area, a low impurity density and a conductivity modulation area, respectively, of an n type on one another sequentially on a substrate of... | 07/05/1994 |
| 5262336 | IGBT process to produce platinum lifetime control For IGBT, MCT or like devices, the substrate is formed with P+, N+ and N- layers and PN diffusions to define body and source regions in the N-layer and a MOS-gated channel at the upper surface. The N-layer is sized and doped (~1014 /cm3 | 11/16/1993 |
| 5182626 | Insulated gate bipolar transistor and method of manufacturing the same In the present invention, baneful influences such as the reduction of the threshold voltage due to the irradiation of an ionizing radiation such as an electron beam and a light ion beam are removed to practice the lifetime control of an IGBT with good con... | 01/26/1993 |
