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| Number | Title | Issue Date |
| 8188511 | Semiconductor device and method of manufacturing thereof A semiconductor device and a method of forming the semiconductor device include a substrate and an n drift layer on the substrate with an insulator film placed between them. A trench is provided in a section between a p base region and an n buffer layer on the surfa... | 05/29/2012 |
| 7893458 | Semiconductor device having lateral MOS transistor and zener diode A semiconductor device includes: a semiconductor substrate; a lateral MOS transistor disposed in the substrate; a Zener diode disposed in the substrate; and a capacitor disposed in the substrate. The transistor includes a drain and a gate, and the diode and the capa... | 02/22/2011 |
| 7795638 | Semiconductor device with a U-shape drift region A cell of a semiconductor device comprises a substrate of n-type with a trench formed in a portion of a first main surface of the substrate and filled with insulator. Two device-feature regions are formed beneath the first main surface of the substrate, the first on... | 09/14/2010 |
| 7759696 | High-breakdown voltage semiconductor switching device and switched mode power supply apparatus using the same A high-breakdown voltage semiconductor switching device includes a resurf region of a second conductivity type; a base region of a first conductivity type formed to be adjacent to the resurf region; an emitter/source region of the second conductivity type formed in ... | 07/20/2010 |
| 7388255 | Semiconductor device having separation region A semiconductor device includes: a semiconductor substrate; a separation region in the substrate; an embedded layer; a channel forming region; a source region; a drain region; a first electrode for the source region; a second electrode for the channel forming region... | 06/17/2008 |
| 7368788 | SRAM cells having inverters and access transistors therein with vertical fin-shaped active regions Complementary metal oxide semiconductor (CMOS) static random access memory (SRAM) cells include at least a first inverter formed in a fin-shaped pattern of stacked semiconductor regions of opposite conductivity type. In some of these embodiments, the first inverter ... | 05/06/2008 |
| 7348630 | Semiconductor device for high frequency uses and manufacturing method of the same The semiconductor device has a semiconductor substrate, gate electrodes formed above the semiconductor substrate, and a pair of impurity diffusion layers formed in a surface layer of the semiconductor substrate at both sides of each of the gate electrodes. The semic... | 03/25/2008 |
| 7342282 | Compact SCR device and method for integrated circuits A semiconductor device and method for electrostatic discharge protection. The semiconductor device includes a first semiconductor controlled rectifier and a second semiconductor controlled rectifier. The first semiconductor controlled rectifier includes a first semi... | 03/11/2008 |
| 7321504 | Static random access memory cell A static random access memory (SRAM) cell having an inverter and a tri-state inverter. An input of the inverter is coupled to an output of the tri-state inverter and an output of the inverter is coupled to an input of the tri-state inverter. The tri-state inverter h... | 01/22/2008 |
| 7294551 | Semiconductor device and method for manufacturing the same A semiconductor device has a gate electrode formed on a P type semiconductor substrate via gate oxide films. A first low concentration (LN type) drain region is made adjacent to one end of the gate electrode. A second low concentration (SLN type) drain region is for... | 11/13/2007 |
| 7275226 | Method of performing latch up check on an integrated circuit design A method of performing latch up check on an integrated circuit (IC) design that comprises rasterizing a conductor region shape and contact shapes and iteratively expanding the contact shapes within the conductor region shape using a cellular algorithm. Direction val... | 09/25/2007 |
| 7268373 | Thyristor-based memory and its method of operation A semiconductor may contain a plurality of circuits each comprising at least one thyristor having a base region. The base region of at least one of the thyristors has a different doping profile than the others. When a bias circuit is used to bias the thyristors, the... | 09/11/2007 |
| 7230455 | Logic circuits utilizing gated diode sensing A family of logic circuits, called gated diode logic circuits, is disclosed wherein small amplitude signals, typically a fraction of the supply voltage, can be sensed and amplified by applying a small amplitude signal to a gate of a gated diode in a sampling mode an... | 06/12/2007 |
| 7208820 | Substrate having a plurality of I/O routing arrangements for a microelectronic device A substrate is provided for packaging a microelectronic device having a pattern of contacts on the surface thereof. The substrate is formed from a support member having a substantially planar surface, and first, second, and third electrically conductive paths. The e... | 04/24/2007 |
| 7205629 | Lateral super junction field effect transistor A voltage booster transistor with an optimal conducting path formed in widebandgap semiconductors like Silicon Carbide and Diamond, is provided as a power transistor with a voltage rating >200V. Contrary to conventional vertical design of power transistors, a higher... | 04/17/2007 |
| 7196361 | Cascoded bi-directional high voltage ESD protection structure In a high voltage ESD protection solution, a plurality of DIACs are connected together to define a cascaded structure with isolation regions provided to prevent n-well and p-well punch through. An p-ring surrounds the DIACs and provides a ground for the substrate in... | 03/27/2007 |
| 7184312 | One transistor SOI non-volatile random access memory cell One aspect of the present subject matter relates to a memory cell, or more specifically, to a one-transistor SOI non-volatile memory cell. In various embodiments, the memory cell includes a substrate, a buried insulator layer formed on the substrate, and a transisto... | 02/27/2007 |
| 7148543 | Semiconductor chip which combines bulk and SOI regions and separates same with plural isolation regions A semiconductor chip includes a base substrate, a bulk device region having a bulk growth layer on a part of the base substrate, an SOI device region having a buried insulator on the base substrate and a silicon layer on the buried insulator, and a boundary layer lo... | 12/12/2006 |
| 7141831 | Snapback clamp having low triggering voltage for ESD protection An SCR device having a first P type region disposed in a semiconductor body and electrically connected to anode terminal of the device. At least one N type region is also disposed in the body adjacent the first P type region so as to form a PN junction having a widt... | 11/28/2006 |
| 7141832 | Semiconductor device and capacitance regulation circuit According to an embodiment of the invention, there is provided a semiconductor device comprising: a semiconductor element having a first main electrode, a second main electrode and a control electrode, a current flowing between the first and second main electrodes b... | 11/28/2006 |
| 7135745 | Fin thyristor-based semiconductor device A semiconductor device having a thyristor-based device and a pass device exhibits characteristics that may include, for example, resistance to short channel effects that occur when conventional MOSFET devices are scaled smaller in connection with advancing technolog... | 11/14/2006 |
| 7135738 | Modular bipolar-CMOS-DMOS analog integrated circuit and power transistor technology A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each o... | 11/14/2006 |
| 7130216 | One-device non-volatile random access memory cell One aspect of the present subject matter relates to a one-device non-volatile memory cell. The memory cell includes a body region, a first diffusion region and a second diffusion region formed in the body region. A channel region is formed in the body region between... | 10/31/2006 |
| 7122861 | Semiconductor device and manufacturing method thereof The present invention relates to a semiconductor device including a high withstand voltage MOS transistor and a manufacturing method thereof. The semiconductor device according to the present invention includes a MOS transistor in which a second-conductivity type so... | 10/17/2006 |
| 7109533 | Electrostatic discharge protection device There is provided an electrostatic discharge protection device comprising a P conductive type first P well region 101 formed in a P type epitaxial layer 31 being deposited on a surface of a P+ substrate 30 having a prescribed thickness, an N con... | 09/19/2006 |
| 7105386 | High density SRAM cell with latched vertical transistors High density static memory cells and arrays containing gated lateral bipolar transistors which can be latched in a bistable on state. Each transistor memory cell includes two gates which are pulse biased during the write operation to latch the cell. Also provided is... | 09/12/2006 |
| 7091557 | Semiconductor component with increased dielectric strength and/or reduced on resistance The invention relates to a semiconductor component having a first semiconductor zone of a first conduction type, a second semiconductor zone of a second conduction type and a drift zone arranged between the first and second semiconductor zones, which drift zone has ... | 08/15/2006 |
| 7087961 | Semiconductor device with reduced on-state resistance To enable the reduction of ON-state resistance in a state in which the withstand voltage is secured, a semiconductor device according to the invention is provided with a gate electrode formed so that the gate electrode ranges from a gate oxide film formed on an N-ty... | 08/08/2006 |
| 7067852 | Electrostatic discharge (ESD) protection structure An ESD protection structure includes a semiconductor substrate of a first conductivity type, and first and second well regions of a second conductivity type disposed in the substrate. The first and second well regions are separated by a gap region of the substrate. ... | 06/27/2006 |
| 7067970 | Light emitting device A light emission device has an emitter made of a dielectric material, a cathode electrode disposed on a surface of the emitter, an anode electrode disposed on a reverse surface of the emitter, and a pulse generation source for applying a drive voltage between the ca... | 06/27/2006 |
| 7045830 | High-voltage diodes formed in advanced power integrated circuit devices A diode-connected lateral transistor on a substrate of a first conductivity type includes a vertical parasitic transistor through which a parasitic substrate leakage current flows. Means for shunting at least a portion of the flow of parasitic substrate leakage curr... | 05/16/2006 |
| 7042027 | Gated lateral thyristor-based random access memory cell (GLTRAM) One aspect of the present subject matter relates to a memory cell, or more specifically, to a scalable GLTRAM cell that provides DRAM-like density and SRAM-like performance. According to various embodiments, the memory cell includes an access transistor and a gated,... | 05/09/2006 |
| 7034358 | Vertical transistor, and a method for producing a vertical transistor The present invention relates to a method for producing a vertical transistor, and to a vertical transistor. A sacrificial gate oxide and a sacrificial gate electrode are used during the production of the vertical transistor to makes it possible to considerably redu... | 04/25/2006 |
| 7029956 | Memory system capable of operating at high temperatures and method for fabricating the same A memory system having a plurality of T-RAM cells arranged in an array is presented where each T-RAM cell has dual vertical devices and is fabricated over a SiC substrate. Each T-RAM cell has a vertical thyristor and a vertical transfer gate. The top surface of each... | 04/18/2006 |
| 7020030 | SRAM cell with horizontal merged devices A merged structure SRAM cell is provided that includes a first transistor and a second transistor. The second transistor gate forms a load resistor for the first transistor and the first transistor gate forms a load resistor for the second transistor. Also provided ... | 03/28/2006 |
| 7012301 | Trench lateral power MOSFET and a method of manufacturing the same A semiconductor device is provided that can be manufactured by a simpler process than a conventional lateral trench power MOSFET for use with an 80V breakdown voltage, and which has a lower device pitch and lower on-state resistance per unit area than a conventional... | 03/14/2006 |
| 6972237 | Lateral heterojunction bipolar transistor and method of manufacture using selective epitaxial growth A method for manufacturing a heterojunction bipolar transistor is provided. An intrinsic collector structure is formed on a substrate. An extrinsic base structure partially overlaps the intrinsic collector structure. An intrinsic base structure is formed adjacent th... | 12/06/2005 |
| 6963109 | Semiconductor device and method for manufacturing the same A semiconductor device has a gate electrode formed on a P type semiconductor substrate via gate oxide films. A first low concentration (LN type) drain region is made adjacent to one end of the gate electrode. A second low concentration (SLN type) drain region is for... | 11/08/2005 |
| 6936866 | Semiconductor component A vertical or lateral semiconductor component derives a signal from a high load voltage. This signal can be used directly for driving the semiconductor component or, alternatively, a control device. ... | 08/30/2005 |
| 6921688 | Method of and apparatus for integrating flash EPROM and SRAM cells on a common substrate A system for and a method of integrating SRAM cells and flash EPROM cells onto a single silicon substrate includes an area on the silicon substrate where a local oxidation of silicon (LOCOS) isolation technique is implemented and another area on the same silicon sub... | 07/26/2005 |
