Did You Know...
...Chester Carlson was a patent agent who tired of having to make multiple copies of patent applications using the only duplication method available at the time: carbon paper. In 1959 he came up with a new copying system and took it to IBM for evaluation. The "experts" at IBM determined potential sales to be only 5,000 units because people wouldn't want to use a bulky machine when they had carbon paper. Carlson's invention was the xerography process, the company founded on the system is Xerox.
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| Number | Title | Issue Date |
| 8159001 | Graded junction high voltage semiconductor device A graded junction space decreasing an implant concentration gradient between n-well and p-well regions of a semiconductor device is provided for enhancing breakdown voltage in high voltage applications. Split or unified FOX regions may be provided overlapping with t... | 04/17/2012 |
| 7994535 | Semiconductor device including a JFET having a short-circuit preventing layer To improve the surge resistance of J-FET, a P-type epitaxial layer 2 and an N-type epitaxial layer 3 are formed on a P++-conductive substrate 1; N+-conductive source diffusion layer 4 and drain diffusion layer 5 | 08/09/2011 |
| 7928469 | MOSFET and method for manufacturing MOSFET The present invention provides a MOSFET and so forth that offer high breakdown voltage and low on-state loss (high channel mobility and low gate threshold voltage) and that can easily achieve normally OFF. A drift layer 2 of a MOSFET made of silicon carbide a... | 04/19/2011 |
| 7838900 | Single-chip common-drain JFET device and its applications A single-chip common-drain JFET device comprises a Drain, two gates and two source arranged such that two common-drain JFETs are formed therewith. Due to the two JFETs merged within a single chip, no wire bonding connection is needed therebetween, thereby without pa... | 11/23/2010 |
| 7838901 | Single-chip common-drain JFET device and its applications A single-chip common-drain JFET device comprises a drain, two gates and two source arranged such that two common-drain JFETs are formed therewith. Due to the two JFETs merged within a single chip, no wire bonding connection is needed therebetween, thereby without pa... | 11/23/2010 |
| 7838902 | Single-chip common-drain JFET device and its applications A single-chip common-drain JFET device comprises a drain, two gates and two source arranged such that two common-drain JFETs are formed therewith. Due to the two JFETs merged within a single chip, no wire bonding connection is needed therebetween, thereby without pa... | 11/23/2010 |
| 7834376 | Power semiconductor switch A SiC JFET that includes a plurality of trenches formed in a SiC semiconductor body of one conductivity each trench having a region of another conductivity formed in the bottom and sidewalls thereof. ... | 11/16/2010 |
| 7768033 | Single-chip common-drain JFET device and its applications A single-chip common-drain JFET device comprises a drain, two gates and two source arranged such that two common-drain JFETs are formed therewith. Due to the two JFETs merged within a single chip, no wire bonding connection is needed therebetween, thereby without pa... | 08/03/2010 |
| 7759695 | Single-chip common-drain JFET device and its applications A single-chip common-drain JFET device comprises a drain, two gates and two source arranged such that two common-drain JFETs are formed therewith. Due to the two JFETs merged within a single chip, no wire bonding connection is needed therebetween, thereby without pa... | 07/20/2010 |
| 7687825 | Insulated gate bipolar conduction transistors (IBCTS) and related methods of fabrication Insulated gate bipolar conduction transistors (IBCTs) are provided. The IBCT includes a drift layer having a first conductivity type. An emitter well region is provided in the drift layer and has a second conductivity type opposite the first conductivity type. A wel... | 03/30/2010 |
| 7642566 | Scalable process and structure of JFET for small and decreasing line widths A scalable device structure and process for forming a normally off JFET with 45 NM linewidths or less. The contacts to the source, drain and gate areas are formed by forming a layer of oxide of a thickness of less than 1000 angstroms, and, preferably 500 angstroms o... | 01/05/2010 |
| 7535032 | Single-chip common-drain JFET device and its applications A single-chip common-drain JFET device comprises a drain, two gates and two source arranged such that two common-drain JFETs are formed therewith. Due to the two JFETs merged within a single chip, no wire bonding connection is needed therebetween, thereby without pa... | 05/19/2009 |
| 7508013 | Versatile system for cross-lateral junction field effect transistor The present, invention provides a system for providing a cross-lateral junction field effect transistor (114) having desired high-performance desired voltage, frequency or current characteristics. The cross-lateral transistor is formed on a commercial semicon... | 03/24/2009 |
| 7378688 | Method and apparatus for a low noise JFET device on a standard CMOS process A microelectric product and the method for manufacturing the product are provided. A source and drain are spaced from one another in a first direction and are connected to opposing ends of a channel to provide a set voltage. First and second gates are spaced from on... | 05/27/2008 |
| 7365373 | Thyristor-type memory device A thyristor device can be used to implement a variety of semiconductor memory circuits, including high-density memory-cell arrays and single cell circuits. In one example embodiment, the thyristor device includes doped regions of opposite polarity, and a first word ... | 04/29/2008 |
| 7348228 | Deep buried channel junction field effect transistor (DBCJFET) A junction field effect transistor (JFET) is fashioned where a channel of transistor is buried deeply within the workpiece within which the JFET is formed. Burying the channel below the surface of the workpiece and/or away from overlying conductive materials distanc... | 03/25/2008 |
| 7348612 | Metal-semiconductor field effect transistors (MESFETs) having drains coupled to the substrate and methods of fabricating the same The present invention provides a unit cell of a metal-semiconductor field-effect transistor (MESFET). The unit cell of the MESFET includes a MESFET having a source region, a drain region and a gate contact. The gate contact is disposed between the source region and ... | 03/25/2008 |
| 7342281 | Electrostatic discharge protection circuit using triple welled silicon controlled rectifier Provided is an electrostatic discharge (ESD) protection circuit using a silicon controlled rectifier (SCR), which is applied to a semiconductor integrated circuit (IC). A semiconductor substrate has a triple well structure such that a bias is applied to a p-well cor... | 03/11/2008 |
| 7338878 | Method for forming capacitor in semiconductor device Upon a deep-hole capacitor fabrication, a hole is formed in an insulator layer, and then a film of a conductive material is formed on the insulator layer and on the whole inner surface of the hole. The film and the insulator layer are exposed to a chemical-mechanica... | 03/04/2008 |
| 7339206 | Field effect transistor including a group III-V compound semiconductor layer A field effect transistor (FET) includes a first semiconductor layer and a second semiconductor layer, the second semiconductor layer being formed on the first semiconductor layer and having a band gap energy greater than that of the first semiconductor layer. The f... | 03/04/2008 |
| 7335952 | Semiconductor device and manufacturing method therefor To provide a semiconductor device that permits free setting of characteristics of individual semiconductor elements which are mixedly mounted and have different characteristics, and is free of steps between formed semiconductor elements, in a manufacturing method fo... | 02/26/2008 |
| 7335928 | Semiconductor device having a metal conductor in ohmic contact with the gate region on the bottom of each the first groove A silicon carbide semiconductor device such as JFET, SIT and the like is provided for accomplishing a reduction in on-resistance and high-speed switching operations. In the JFET or SIT which turns on/off a current with a depletion layer extending in a channel betwee... | 02/26/2008 |
| 7314801 | Semiconductor device having a surface conducting channel and method of forming A semiconductor device including a metal oxide layer, a channel area of the metal oxide layer, a preservation layer formed on the channel area of the metal oxide layer, and at least two channel contacts coupled to the channel area of the metal oxide layer, and a met... | 01/01/2008 |
| 7312481 | Reliable high-voltage junction field effect transistor and method of manufacture therefor The present invention provides a high-voltage junction field effect transistor (JFET), a method of manufacture and an integrated circuit including the same. One embodiment of the high-voltage junction field effect transistor (JFET) (300) includes a well regio... | 12/25/2007 |
| 7294550 | Method of fabricating metal oxide semiconductor device A method of fabricating an MOS device is described. A substrate doped a first type dopant is provided as a drain. A first type epitaxial layer is formed on the substrate and is patterned with a trench to form several islands. A gate dielectric layer is than formed o... | 11/13/2007 |
| 7291874 | Laser dicing apparatus for a gallium arsenide wafer and method thereof The present invention discloses a laser dicing apparatus for a gallium arsenide wafer and a method thereof, wherein firstly, a gallium arsenide wafer is stuck onto a holding film; next, the gallium arsenide wafer together with the holding film is disposed on a worki... | 11/06/2007 |
| 7288800 | Versatile system for cross-lateral junction field effect transistor The present invention provides a system for providing a cross-lateral junction field effect transistor (114) having desired high-performance desired voltage, frequency or current characteristics. The cross-lateral transistor is formed on a commercial semicond... | 10/30/2007 |
| 7279368 | Method of manufacturing a vertical junction field effect transistor having an epitaxial gate A vertical junction field effect transistor includes a trench formed in an epitaxial layer. The trench surrounds a channel region of the epitaxial layer. The channel region may have a graded or uniform dopant concentration profile. An epitaxial gate structure is for... | 10/09/2007 |
| 7271446 | Ultra-thin channel device with raised source and drain and solid source extension doping The inventive method for forming thin channel MOSFETS comprises: providing a structure including at least a substrate having a layer of semiconducting material atop an insulating layer and a gate region formed atop the layer of semiconducting material; forming a con... | 09/18/2007 |
| 7268378 | Structure for reduced gate capacitance in a JFET A junction field effect transistor (JFET) with a reduced gate capacitance. A gate definition spacer is formed on the wall of an etched trench to establish the lateral extent of an implanted gate region for a JFET. After implant, the gate is annealed. In addition to ... | 09/11/2007 |
| 7262442 | Triac operating in quadrants Q1 and Q4 A triac including on its front surface side an autonomous starting well of the first conductivity type containing a region of the second conductivity type arranged to divide it, in top view, into a first and a second well portion, the first portion being connected t... | 08/28/2007 |
| 7242040 | Lateral trench field-effect transistors in wide bandgap semiconductor materials, methods of making, and integrated circuits incorporating the transistors A junction field effect transistor is described. The transistor is made from a wide bandgap semiconductor material. The device comprises source, channel, drift and drain semiconductor layers, as well as p-type implanted or Schottky gate regions. The source, channel,... | 07/10/2007 |
| 7230283 | Semiconductor device having a metal conductor in ohmic contact with the gate region on the bottom of each groove A silicon carbide semiconductor device such as JFET, SIT and the like is provided for accomplishing a reduction in on-resistance and high-speed switching operations. In the JFET or SIT which turns on/off a current with a depletion layer extending in a channel betwee... | 06/12/2007 |
| 7230275 | Silicon carbide semiconductor device having junction field effect transistor and method for manufacturing the same A silicon carbide semiconductor device includes a substrate and a junction field effect transistor. The transistor includes: a first semiconductor layer disposed on the substrate; a first gate layer disposed on a surface of the first semiconductor layer; a first cha... | 06/12/2007 |
| 7211845 | Multiple doped channel in a multiple doped gate junction field effect transistor A multiple doped channel in a multiple doped gate junction field effect transistor. In accordance with a first embodiment of the present invention, a junction field effect transistor (JFET) circuit structure comprises a vertical channel. The vertical channel compris... | 05/01/2007 |
| 7208774 | Semiconductor optical device In a semiconductor optical device, a first conductive type semiconductor region is provided on a surface of GaAs. The first conductive type semiconductor region has a first region and a second region. An active layer is provided on the first region of the first cond... | 04/24/2007 |
| 7205215 | Fabrication method of thin film transistor The present invention provides a fabrication method of thin film transistor including a step of forming an amorphous silicon layer on a substrate, a step of forming a capping layer on the amorphous silicon layer, a step of forming a metal catalyst layer on the cappi... | 04/17/2007 |
| 7202528 | Normally-off integrated JFET power switches in wide bandgap semiconductors and methods of making Wide bandgap semiconductor devices including normally-off VJFET integrated power switches are described. The power switches can be implemented monolithically or hybridly, and may be integrated with a control circuit built in a single-or multi-chip wide bandgap power... | 04/10/2007 |
| 7183598 | Colors only process to reduce package yield loss Disclosed is an ordered microelectronic fabrication sequence in which color filters are formed by conformal deposition directly onto a photodetector array of a CCD, CID, or CMOS imaging device to create a concave-up pixel surface, and, overlayed with a high transmit... | 02/27/2007 |
| 7164160 | Integrated circuit device with a vertical JFET We disclose the structure of a JFET device, the method of making the device and the operation of the device. The device is built near the top of a substrate. It has a buried layer that is electrically communicable to a drain terminal. It has a channel region over th... | 01/16/2007 |
