Bizarre Patents
Mouse device with a built-in printer
A mouse device for use as an input device of a computer is provided that includes a housing in which recording paper is loadable, and a printer unit provided within the housing for printing on the recording paper print information received from the computer.
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| Number | Title | Issue Date |
| 7999284 | Semiconductor device and optical device module having the same A solid-state imaging device 1 is arranged so that a hollow section 9 is formed between a solid-state imaging element 2 and a covering section 4 and an air path 7 is formed in an adhesive section 5 so as to extend from the h... | 08/16/2011 |
| 7777248 | Semiconductor device for latch-up prevention A semiconductor device is provided for preventing Latch-up in Silicon Controlled Rectifiers (SCRs) when these SCRs become activated. Embodiments of the invention use a natively doped region having high resistance to separate the NPN transistor from the PNP transisto... | 08/17/2010 |
| 7692210 | Intermeshed guard bands for multiple voltage supply structures on an integrated circuit, and methods of making same The present invention is generally directed to intermeshed guard bands for multiple voltage supply regions or structures on an integrated circuit, and methods of making same. In one illustrative embodiment, an integrated circuit is provided that comprises a pluralit... | 04/06/2010 |
| 7667242 | Systems and methods for maximizing breakdown voltage in semiconductor devices Systems and methods for maximizing the breakdown voltage of a semiconductor device are described. In a multiple floating guard ring design, the spacing between two consecutive sets of floating guard rings may increase with their distance from the main junction while... | 02/23/2010 |
| 7663159 | Seal ring corner design Techniques for an integrated circuit device are provided. The integrated circuit device includes a substrate, an active circuit area, and a dielectric layer. A seal ring surrounds the active circuit area. At least one corner area of the integrated circuit includes a... | 02/16/2010 |
| 7649213 | Semiconductor device A semiconductor device includes an SiC substrate, a normal direction of the substrate surface being off from a or direction in an off direction, an SiC layer formed on the SiC substrate, a junction forming region formed in a substantially central port... | 01/19/2010 |
| 7582918 | Semiconductor device with enhanced breakdown voltage In a peripheral portion of an IGBT chip, an intermediate potential electrode (20) is provided between a field plate (14) and a field plate (15) on a field oxide film (13), to surround an IGBT cell. The intermediate potential electrode ( | 09/01/2009 |
| 7576369 | Deep diffused thin photodiodes This invention comprises photodiodes, optionally organized in the form of an array, including p+ deep diffused regions or p+ and n+ deep diffused regions. More specifically, the invention permits one to fabricate thin 4 inch and 6 inch wafer using the physical suppo... | 08/18/2009 |
| 7566915 | Guard ring extension to prevent reliability failures An embodiment of the present invention is a technique to prevent reliability failures in semiconductor devices. A trench is patterned in a polyimide layer over a guard ring having a top metal layer. A passivation layer is etched at bottom of the trench. A capping la... | 07/28/2009 |
| 7566914 | Devices with adjustable dual-polarity trigger- and holding-voltage/current for high level of electrostatic discharge protection in sub-micron mixed signal CMOS/BiCMOS integrated circuits Symmetrical/asymmetrical bidirectional S-shaped I-V characteristics with trigger voltages ranging from 10 V to over 40 V and relatively high holding current are obtained for advanced sub-micron silicided CMOS (Complementary Metal Oxide Semiconductor)/BiCMOS (Bipolar... | 07/28/2009 |
| 7409660 | Method and end cell library for avoiding substrate noise in an integrated circuit A method of avoiding substrate noise in an integrated circuit includes steps of receiving as input an integrated circuit design that includes at least a portion of a block for placement and routing on a substrate and an outer boundary of the block. An end cell is se... | 08/05/2008 |
| 7408206 | Method and structure for charge dissipation in integrated circuits Methods and structures and methods of designing structures for charge dissipation in an integrated circuit on an SOI substrate. A first structure includes a charge dissipation ring around a periphery of the integrated circuit chip and one or more charge dissipation ... | 08/05/2008 |
| 7391093 | Semiconductor device with a guard-ring structure and a field plate formed of polycrystalline silicon film embedded in an insulating film A semiconductor device has a semiconductor device chip with upper and lower terminal electrodes, and upper and lower frames bonded to the upper and lower terminal electrodes, respectively, with solder material, wherein the semiconductor device chip includes: a semic... | 06/24/2008 |
| 7329894 | Semiconductor laser device and semiconductor optical modulator Since the semiconductor devices including a stacked structure of group-III-V alloy semiconductor layers different in the kind of group-V constituent atom form the so-called band line-up of type II, band discontinuity in the heterostructure has impeded smooth transpo... | 02/12/2008 |
| 7326974 | Sensor for measuring a gas concentration or ion concentration A field-effect transistor used as a sensor for measuring a gas or ion concentration utilizes a surface structure such as rings along with surface profiling, for example elevations of the rings and depressions therebetween, to decrease the surface conductivity betwee... | 02/05/2008 |
| 7321145 | Method and apparatus for operating nonvolatile memory cells with modified band structure A nonvolatile memory cell with a charge storage structure is read by measuring current (such as band-to-band current) between the substrate region of the memory cell and at least one of the current carrying nodes of the memory cell. To enhance the operation of the n... | 01/22/2008 |
| 7309883 | Semiconductor device capable of preventing current flow caused by latch-up and method of forming the same A semiconductor device includes first, second, and third wells. The first well is connected to a pad to which an external pin is connected and includes a first-type diffusion region that receives a well bias voltage. The second well is adjacent to the first well, an... | 12/18/2007 |
| 7309628 | Method of forming a semiconductor device A semiconductor device is formed as part of an integrated circuit. The semiconductor device, which is formed in an active semiconductor layer, is surrounded by a guardian that provides a diffusion barrier against contaminants and also provides assistance in avoiding... | 12/18/2007 |
| 7288799 | Semiconductor device and fabrication method thereof A semiconductor device includes a semiconductor substrate, a circuit part formed on and above the semiconductor substrate, a passivation film covering the circuit part, an electrode pad provided outside the circuit part in such a manner that the electrode pad is exp... | 10/30/2007 |
| 7276743 | Retaining ring with conductive portion A retaining ring for use with electrochemical mechanical processing is described. The retaining ring has a generally annular body formed with a conductive portion and a non-conductive portion. The non-conductive portion contacts the substrate during polishing. The c... | 10/02/2007 |
| 7273760 | Semiconductor device and method of manufacturing the same The present invention provides a method of manufacturing a semiconductor device that can inhibit deterioration of the ferroelectric film cased by hydrogen generated in a wiring layer. The method of manufacturing a semiconductor device includes steps of forming the f... | 09/25/2007 |
| 7268421 | Semiconductor chip assembly with welded metal pillar that includes enlarged ball bond A semiconductor chip assembly includes a semiconductor chip that includes a conductive pad, a conductive trace that includes a routing line and a metal pillar, a connection joint that electrically connects the routing line and the pad, and an encapsulant. The chip a... | 09/11/2007 |
| 7238976 | Schottky barrier rectifier and method of manufacturing the same A Schottky barrier rectifier, in accordance with embodiments of the present invention, includes a first conductive layer and a semiconductor. The semiconductor includes a first doped region, a second doped region and a plurality of third doped regions. The second do... | 07/03/2007 |
| 7211896 | Semiconductor device and method of manufacturing the same There is provided a method of manufacturing a semiconductor device in which interconnect capacitance is restrained. The semiconductor device 200 comprises a semiconductor substrate; a second interconnect insulating film 216 constituted of a ladder-type... | 05/01/2007 |
| 7208419 | Method for fabricating semiconductor device The present invention relates to a method for fabricating a semiconductor device. The method comprises the steps of: forming a gate line on a semiconductor substrate; forming a buffer layer and a spacer nitride film on the entire surface of the substrate including t... | 04/24/2007 |
| 7195959 | Thyristor-based semiconductor device and method of fabrication A thyristor-based semiconductor memory device may comprise at least a region thereof, e.g., a p-base region, having high ionization energy impurity, such as a dopant. This high ionization energy impurity within a base region may be operable to compensate for a gain-... | 03/27/2007 |
| 7190009 | Semiconductor device There is provided a semiconductor device in which the thresholds of gate electrodes in transistors can be adjusted together for each of regions having their own functions different from one another. The semiconductor device is provided with: a P-type Si substrate | 03/13/2007 |
| 7169699 | Semiconductor device having a guard ring A semiconductor device has a guard ring in a multilayer interconnection structure, wherein the guard ring includes a conductive wall extending zigzag in a plane parallel with a principal surface of a substrate. ... | 01/30/2007 |
| 7157365 | Semiconductor device having a dummy conductive via and a method of manufacture therefor The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the same. In one aspect, the present invention provides a semiconductor device having a dielectric layer located over a conductive feature an... | 01/02/2007 |
| 7151302 | Method and apparatus for maintaining topographical uniformity of a semiconductor memory array A semiconductor device includes a memory array having a plurality of non-volatile memory cells. Each non-volatile memory cell of the plurality of non-volatile memory cells has a gate stack. The gate stack includes a control gate and a discrete charge storage layer s... | 12/19/2006 |
| 7145211 | Seal ring for mixed circuitry semiconductor devices In mixed-component, mixed-signal, semiconductor devices, selective seal ring isolation from the substrate and its electrical potential is provided in order to segregate noise sensitive circuitry from electrical noise generated by electrically noisy circuitry. Approp... | 12/05/2006 |
| 7138700 | Semiconductor device with guard ring for preventing water from entering circuit region from outside A semiconductor device has a first guard ring surrounding a circuit region, a second ring disposed between the circuit region and the first guard ring, and first connections connecting the first guard ring and the second guard ring to each other. An area sandwiched ... | 11/21/2006 |
| 7135718 | Diode device and transistor device A semiconductor device having improved breakdown voltage is provided. A diode device of the present invention includes relay diffusion layers provided between guard ring portions. Therefore, a depletion layer expanded outward from the guard ring portions except the ... | 11/14/2006 |
| 7132720 | Semiconductor device having guard ring and manufacturing method thereof An interlayer insulation film is etched to form contact holes in an integrated circuit part. At this time, a trench is not formed in a guard ring part. Subsequently, ion implantation is carried out in source/drain regions in a peripheral circuit part for contact com... | 11/07/2006 |
| 7132696 | Intermeshed guard bands for multiple voltage supply structures on an integrated circuit, and methods of making same The present invention is generally directed to intermeshed guard bands for multiple voltage supply regions or structures on an integrated circuit, and methods of making same. In one illustrative embodiment, an integrated circuit is provided that comprises a pluralit... | 11/07/2006 |
| 7132316 | After deposition method of thinning film to reduce pinhole defects A method of forming a thin film is provided in which a film having a first thickness is deposited over a substrate, wherein the first thickness is greater than a thickness at which the initially deposited film begins to dewet from the substrate. The initially deposi... | 11/07/2006 |
| 7129544 | Vertical compound semiconductor field effect transistor structure In one embodiment, a compound semiconductor vertical FET device (11) includes a first trench (29) formed in a body of semiconductor material (13), and a second trench (34) formed within the first trench (29) to define a channel reg... | 10/31/2006 |
| 7115997 | Seedless wirebond pad plating An integrated circuit (IC) chip, semiconductor wafer with IC chips in a number of die locations and a method of making the IC chips on the wafer. The IC chips have plated chip interconnect pads. Each plated pad includes a noble metal plated layer electroplated to a ... | 10/03/2006 |
| 7071516 | Semiconductor device and driving circuit for semiconductor device A PMOS transistor (Q2) provided for developing a short circuit between the base and emitter of an N-type IGBT during turn-OFF includes a P diffusion region (5), a P diffusion region (6), and a conductive film (10) and a second gate electr... | 07/04/2006 |
| 7053356 | Photodetection cell and laser pulse detector having a cascoded inverting amplifier looped back through a slow follower type feedback Photodetection cell and laser pulse detector furnished with such a cell, as well as laser pulse detection device comprising a matrix of such detectors. The photodetection cell (1) is embodied in the form of an integrated circuit and comprises a photose... | 05/30/2006 |
